Use the DBCN SBI extension to implement a debug console.
Make it the default for S-mode RISC-V.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>

Waiting 150us TC bit couldn't be enough.

If TFA lets 16 bits in USART fifo, we has to wait 16 times 87 us (time
of 10 bits (1 byte in most use cases) at a baud rate of 115200).

Fixes: b4dbc5d65a67 ("serial: stm32: Wait TC bit before performing initialization")

Signed-off-by: Valentin Caron <valentin.caron@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>

This patch ensures driver private data being fully initialized in
_debug_uart_init which is not covered by .priv_auto ops.

Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Reviewed-by: Stefan Roese <sr@denx.de>

Before this change the FR_TXFF (Transmit FIFO full) bit (5 in
HW_UARTDBG_FR) has been used to assess if there is still data pending
to be sent via UART.

This approach is problematic, as it may happen that serial is in the
middle of transmission (so the TX FIFO is NOT full anymore) and this
test returns true infinitely. As a result, for example in _serial_flush()
DM serial function we are locked in endless while().

The fix here is to test explicitly if the TX FIFO is empty.

Signed-off-by: Lukasz Majewski <lukma@denx.de>

This commit prepares the pl01x serial driver to be used with
SPL_OF_PLATDATA enabled.

Signed-off-by: Lukasz Majewski <lukma@denx.de>

Before this change, building this driver for SPL with enabled SPL_DM_SERIAL
was problematic, as '-Wunused-const-variable=' warning was visible.

Now, the code is only considered when u-boot proper is build.

Signed-off-by: Lukasz Majewski <lukma@denx.de>

To avoid spurious chars, BRR register must only be written when
USART is disabled.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>

In case there is still chars from previous bootstage to transmit, wait
for TC (Transmission Complete) bit to be set which ensure that the last
data written in the USART_TDR has been transmitted out of the shift
register.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>

According to the dm_serial_ops documentation, pending() should:
> @return number of waiting characters, 0 for none, -ve on error

And:
> It is acceptable to return 1 if an indeterminant number
> of characters is waiting.

With the current implementation, we have:
* FIFO is full           -> pending() returns 0
* FIFO is partially used -> pending() returns 1
* FIFO is empty          -> pending() returns 1

This is not the same as what the documentation requires.

Moreover, since [1], arm reset now flushes all console devices
(including serial) before the cpu gets reset.
Because of the flawed logic:

  => reset # user calls reset
  flush() is called
  _serial_flush() is called
  ops->pending(dev, false) # never returns false
  # board hangs indefinitely without resetting.

Fix it by using AML_UART_TX_EMPTY instead of AML_UART_TX_FULL.

[1] commit c5f4cdb8eb60 ("console: Use flush() before panic and reset"),

Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Acked-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20230606-fix-meson-serial-pending-v1-1-6a54d4a01f76@baylibre.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>

Add trivial driver for the MXS AUART IP. This is the other UART IP
present in i.MX23 and i.MX28, used to drive the non-DUART ports.

Signed-off-by: Marek Vasut <marex@denx.de>