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<title>u-boot.git/drivers/serial, branch v2023.10-rc2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/serial?h=v2023.10-rc2</id>
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<updated>2023-08-03T13:40:49Z</updated>
<entry>
<title>serial: mtk: initial priv data before using</title>
<updated>2023-08-03T13:40:49Z</updated>
<author>
<name>Weijie Gao</name>
<email>weijie.gao@mediatek.com</email>
</author>
<published>2023-07-19T09:16:07Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=0fd96bf224c1af7f8fc3bbdc814eba0349d0c334'/>
<id>urn:sha1:0fd96bf224c1af7f8fc3bbdc814eba0349d0c334</id>
<content type='text'>
This patch ensures driver private data being fully initialized in
_debug_uart_init which is not covered by .priv_auto ops.

Signed-off-by: Sam Shih &lt;sam.shih@mediatek.com&gt;
Signed-off-by: Weijie Gao &lt;weijie.gao@mediatek.com&gt;
Reviewed-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>serial: pl01x: Modify pending callback to test if transmit FIFO is empty</title>
<updated>2023-07-11T12:40:04Z</updated>
<author>
<name>Lukasz Majewski</name>
<email>lukma@denx.de</email>
</author>
<published>2023-05-19T10:43:53Z</published>
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<id>urn:sha1:a21789194873d768ba829eb0169c7f0e3ceb85ef</id>
<content type='text'>
Before this change the FR_TXFF (Transmit FIFO full) bit (5 in
HW_UARTDBG_FR) has been used to assess if there is still data pending
to be sent via UART.

This approach is problematic, as it may happen that serial is in the
middle of transmission (so the TX FIFO is NOT full anymore) and this
test returns true infinitely. As a result, for example in _serial_flush()
DM serial function we are locked in endless while().

The fix here is to test explicitly if the TX FIFO is empty.

Signed-off-by: Lukasz Majewski &lt;lukma@denx.de&gt;
</content>
</entry>
<entry>
<title>serial: pl01x: Prepare the driver to support SPL_OF_PLATDATA</title>
<updated>2023-07-11T12:40:04Z</updated>
<author>
<name>Lukasz Majewski</name>
<email>lukma@denx.de</email>
</author>
<published>2023-05-19T10:43:52Z</published>
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<id>urn:sha1:875752adc8b6a25ebaf9f45cb3fd206065a80f0e</id>
<content type='text'>
This commit prepares the pl01x serial driver to be used with
SPL_OF_PLATDATA enabled.

Signed-off-by: Lukasz Majewski &lt;lukma@denx.de&gt;
</content>
</entry>
<entry>
<title>serial: pl01x: Change OF_CONTROL to OF_REAL</title>
<updated>2023-07-11T12:40:04Z</updated>
<author>
<name>Lukasz Majewski</name>
<email>lukma@denx.de</email>
</author>
<published>2023-05-19T10:43:51Z</published>
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<id>urn:sha1:fdef5e1502a6b847acf3252c0f21739a3a4e181c</id>
<content type='text'>
Before this change, building this driver for SPL with enabled SPL_DM_SERIAL
was problematic, as '-Wunused-const-variable=' warning was visible.

Now, the code is only considered when u-boot proper is build.

Signed-off-by: Lukasz Majewski &lt;lukma@denx.de&gt;
</content>
</entry>
<entry>
<title>serial: stm32: BRR must be set only when usart is disable</title>
<updated>2023-06-16T09:29:29Z</updated>
<author>
<name>Patrice Chotard</name>
<email>patrice.chotard@foss.st.com</email>
</author>
<published>2023-05-31T06:01:31Z</published>
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<id>urn:sha1:8ab9e8ffdf0977ce5101a4d71b75655667eced5e</id>
<content type='text'>
To avoid spurious chars, BRR register must only be written when
USART is disabled.

Signed-off-by: Patrice Chotard &lt;patrice.chotard@foss.st.com&gt;
Reviewed-by: Patrick Delaunay &lt;patrick.delaunay@foss.st.com&gt;
</content>
</entry>
<entry>
<title>serial: stm32: Wait TC bit before performing initialization</title>
<updated>2023-06-16T09:29:29Z</updated>
<author>
<name>Patrice Chotard</name>
<email>patrice.chotard@foss.st.com</email>
</author>
<published>2023-05-31T06:01:30Z</published>
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<id>urn:sha1:b4dbc5d65a67456db9cfe874d123e1c87860301d</id>
<content type='text'>
In case there is still chars from previous bootstage to transmit, wait
for TC (Transmission Complete) bit to be set which ensure that the last
data written in the USART_TDR has been transmitted out of the shift
register.

Signed-off-by: Patrice Chotard &lt;patrice.chotard@foss.st.com&gt;
Reviewed-by: Patrick Delaunay &lt;patrick.delaunay@foss.st.com&gt;
</content>
</entry>
<entry>
<title>serial: meson: fix meson_serial_pending() tx logic</title>
<updated>2023-06-07T08:09:20Z</updated>
<author>
<name>Mattijs Korpershoek</name>
<email>mkorpershoek@baylibre.com</email>
</author>
<published>2023-06-06T16:07:48Z</published>
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<id>urn:sha1:afa85a2247297d660a63295bfbdd6e24e8e56902</id>
<content type='text'>
According to the dm_serial_ops documentation, pending() should:
&gt; @return number of waiting characters, 0 for none, -ve on error

And:
&gt; It is acceptable to return 1 if an indeterminant number
&gt; of characters is waiting.

With the current implementation, we have:
* FIFO is full           -&gt; pending() returns 0
* FIFO is partially used -&gt; pending() returns 1
* FIFO is empty          -&gt; pending() returns 1

This is not the same as what the documentation requires.

Moreover, since [1], arm reset now flushes all console devices
(including serial) before the cpu gets reset.
Because of the flawed logic:

  =&gt; reset # user calls reset
  flush() is called
  _serial_flush() is called
  ops-&gt;pending(dev, false) # never returns false
  # board hangs indefinitely without resetting.

Fix it by using AML_UART_TX_EMPTY instead of AML_UART_TX_FULL.

[1] commit c5f4cdb8eb60 ("console: Use flush() before panic and reset"),

Signed-off-by: Mattijs Korpershoek &lt;mkorpershoek@baylibre.com&gt;
Acked-by: Neil Armstrong &lt;neil.armstrong@linaro.org&gt;
Link: https://lore.kernel.org/r/20230606-fix-meson-serial-pending-v1-1-6a54d4a01f76@baylibre.com
Signed-off-by: Neil Armstrong &lt;neil.armstrong@linaro.org&gt;
</content>
</entry>
<entry>
<title>serial: mxs: Add MXS AUART driver</title>
<updated>2023-05-21T14:54:41Z</updated>
<author>
<name>Marek Vasut</name>
<email>marex@denx.de</email>
</author>
<published>2023-05-06T14:43:31Z</published>
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<id>urn:sha1:ff476897ed698eae1fa439d52b30694a2b40464a</id>
<content type='text'>
Add trivial driver for the MXS AUART IP. This is the other UART IP
present in i.MX23 and i.MX28, used to drive the non-DUART ports.

Signed-off-by: Marek Vasut &lt;marex@denx.de&gt;
</content>
</entry>
<entry>
<title>x86: Allow locating the UART from ACPI tables</title>
<updated>2023-05-11T02:25:29Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2023-05-04T22:55:00Z</published>
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<id>urn:sha1:b29dbf98baa35441ad01957bb2317cb4f70f390f</id>
<content type='text'>
When coreboot does not pass a UART in its sysinfo struct, there is no
easy way to find it out.

Since coreboot does not actually init the serial device when serial is
disabled, it is not possible to make it add this information to the
sysinfo table.

Add a way to obtain this information from the DBG2 ACPI table, which is
normally set up by coreboot.

For now this only supports a memory-mapped 16550-style UART.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>Merge tag 'u-boot-rockchip-20230509' of https://source.denx.de/u-boot/custodians/u-boot-rockchip</title>
<updated>2023-05-09T16:45:49Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2023-05-09T16:45:49Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=0a9a4384c1483a88776bca38e28f09be51161034'/>
<id>urn:sha1:0a9a4384c1483a88776bca38e28f09be51161034</id>
<content type='text'>
- Rockchip NFC driver update and dev addr pointer api update;
- use standard dr_mode for usb driver;
- rock pi boards dts update;
- Add rk3566 Anbernic boards;
- Misc fixes for drivers;
</content>
</entry>
</feed>
