int is not sufficient to hold and test the return from an EFI function
call. Use efi_status_t instead so that the test can work as expected.
This issue was found by Smatch.
Fixes: 275854baeeec ("efi: Add a serial driver")
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
The NULL check for priv in qcom_geni_serial_poll_bit serves no useful prupose as too much other code surrounding it relies on priv being valid. Remove the NULL check for priv and other related code. This issue was found by Smatch. Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org> Link: https://lore.kernel.org/r/20250811-serial_msm_geni-v1-2-4499179491bc@linaro.org Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
In msm_serial_setbrg if the call to get_clk_div_rate fails then there will not have been an assignment to clk_div which will lead to the call to geni_serial_baud using an uninitialised value. Check for an error from get_clk_div_rate and return an error code if so. This issue was found by Smatch. Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org> Reviewed-by: Casey Connolly <casey.connolly@linaro.org> Link: https://lore.kernel.org/r/20250811-serial_msm_geni-v1-1-4499179491bc@linaro.org Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
With the removal of the last i.MX31 platform we can remove the rest of
the underlying architecture code as well.
Fixes: f247354708ec ("arm: Remove mx31pdk board")
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
The high-speed UART from MediaTek supports baudrate accuracy compensation when using high-speed mode 3. This is done by calculating the first digit of the fraction part of sample count value. The fraction value will be then used as the reference to insert 0 to 10 sample cycle(s) to one frame (assume that frame format is 8n1, i.e. 10 bits per frame). The fracdiv_[l/m] registers are used to determine whether a bit in one frame should be inserted with one sample cycle. With typical 40MHz source clock, the actual baudrates with/without accuracy compensation are: Ideal w/o compensation w/ compensation ======== ================ =============== 9600 9603 9600 115200 114942 115207 921600 930232 921659 3000000 3076923 3007519 Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Fix UART register names and offsets according to the programming guide to allow implementing some enhanced features. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Add useful default debug uart values for all Versal platforms to simplify
and speed up debug uart enabling.
The similar change has been done for Zynq/ZynqMP by commit ad55d99e3cc3
("serial: Setup serial base and freq for zynq/zynqmp").
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/86edf3dbb6de16337aac36f5121f306f83149fc0.1741868624.git.michal.simek@amd.com
Tom Rini <trini@konsulko.com> says: This series switches to always using $(PHASE_) in Makefiles when building rather than $(PHASE_) or $(XPL_). It also starts on documenting this part of the build, but as a follow-up we need to rename doc/develop/spl.rst and expand on explaining things a bit. Link: https://lore.kernel.org/r/20250401225851.1125678-1-trini@konsulko.com
It is confusing to have both "$(PHASE_)" and "$(XPL_)" be used in our Makefiles as part of the macros to determine when to do something in our Makefiles based on what phase of the build we are in. For consistency, bring this down to a single macro and use "$(PHASE_)" only. Signed-off-by: Tom Rini <trini@konsulko.com>
Simon Glass <sjg@chromium.org> says: The membuff implementation curently has no tests. It also assumes that head and tail can never correspond unless the buffer is empty. This series provides a compile-time flag to support a 'full' flag. It also adds some tests of the main routines. The data structure is also renamed to membuf which fits better with U-Boot. There may be some cases in the code which could be optimised a little, but the implementation is functional. Link: https://lore.kernel.org/r/20250318152059.1464369-1-sjg@chromium.org