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<title>u-boot.git/drivers/soc/soc_amd_versal2.c, branch master</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
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<entry>
<title>drivers: firmware: update xilinx_pm_request to support max payload</title>
<updated>2025-10-09T07:07:03+00:00</updated>
<author>
<name>Naman Trivedi</name>
<email>naman.trivedimanojbhai@amd.com</email>
</author>
<published>2025-08-28T13:42:22+00:00</published>
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Currently xilinx_pm_request API supports four u32 payloads. However the
legacy SMC format supports five u32 request payloads and extended SMC
format supports six u32 request payloads. Add support for the same in
xilinx_pm_request API. Also add two dummy arguments to all the callers
of xilinx_pm_request.

The TF-A always fills seven u32 return payload so add support
for the same in xilinx_pm_request API.

Signed-off-by: Naman Trivedi &lt;naman.trivedimanojbhai@amd.com&gt;
Signed-off-by: Venkatesh Yadav Abbarapu &lt;venkatesh.abbarapu@amd.com&gt;
Acked-by: Senthil Nathan Thangaraj &lt;senthilnathan.thangaraj@amd.com&gt;
Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
Link: https://lore.kernel.org/r/5ae6b560741f3ca8b89059c4ebb87acf75b4718e.1756388537.git.michal.simek@amd.com
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<pre>
Currently xilinx_pm_request API supports four u32 payloads. However the
legacy SMC format supports five u32 request payloads and extended SMC
format supports six u32 request payloads. Add support for the same in
xilinx_pm_request API. Also add two dummy arguments to all the callers
of xilinx_pm_request.

The TF-A always fills seven u32 return payload so add support
for the same in xilinx_pm_request API.

Signed-off-by: Naman Trivedi &lt;naman.trivedimanojbhai@amd.com&gt;
Signed-off-by: Venkatesh Yadav Abbarapu &lt;venkatesh.abbarapu@amd.com&gt;
Acked-by: Senthil Nathan Thangaraj &lt;senthilnathan.thangaraj@amd.com&gt;
Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
Link: https://lore.kernel.org/r/5ae6b560741f3ca8b89059c4ebb87acf75b4718e.1756388537.git.michal.simek@amd.com
</pre>
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</content>
</entry>
<entry>
<title>arm64: versal2: Show major and minor silicon version</title>
<updated>2025-03-03T15:09:59+00:00</updated>
<author>
<name>Michal Simek</name>
<email>michal.simek@amd.com</email>
</author>
<published>2025-02-18T12:43:07+00:00</published>
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ES1 silicon is 0x10 (16) and production is 0x20 (32) but correct number to
see are v1.0 or v2.0 instead of v16 or v32.

Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
Link: https://lore.kernel.org/r/20095339334fe07f373ffae3bdbfec51f5a00dc7.1739882585.git.michal.simek@amd.com
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<pre>
ES1 silicon is 0x10 (16) and production is 0x20 (32) but correct number to
see are v1.0 or v2.0 instead of v16 or v32.

Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
Link: https://lore.kernel.org/r/20095339334fe07f373ffae3bdbfec51f5a00dc7.1739882585.git.michal.simek@amd.com
</pre>
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</entry>
<entry>
<title>soc: versal2: Add SoC driver for AMD Versal Gen 2</title>
<updated>2024-06-17T14:02:29+00:00</updated>
<author>
<name>Michal Simek</name>
<email>michal.simek@amd.com</email>
</author>
<published>2024-05-29T14:47:59+00:00</published>
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<content type='text'>
Communication is happening via firmware interface (SMC) or via direct
register reading if firmware driver is not available.

Also enable it via defconfig.

Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
Link: https://lore.kernel.org/r/22cf9c765e47ab03dbf2b8363e6626e809113432.1716994063.git.michal.simek@amd.com
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<pre>
Communication is happening via firmware interface (SMC) or via direct
register reading if firmware driver is not available.

Also enable it via defconfig.

Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
Link: https://lore.kernel.org/r/22cf9c765e47ab03dbf2b8363e6626e809113432.1716994063.git.michal.simek@amd.com
</pre>
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