u-boot.git/drivers/spi/Makefile, branch next Unnamed repository; edit this file 'description' to name the repository. spi: nxp_xspi: Add new driver for NXP XSPI controller 2026-03-16T21:44:58+00:00 Alice Guo alice.guo@nxp.com 2026-03-12T00:57:22+00:00 2875ae59691cd6d371dfa36a43b7ce37c168dcf3 Add new driver to support NXP XSPI controller for NOR and NAND flash. XSPI controller also uses a programmable sequence engine to provide flexibility to support existing and future memory devices. It supports single, dual, quad, octal modes of operation. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Alice Guo <alice.guo@nxp.com> 
Add new driver to support NXP XSPI controller for NOR and NAND flash.
XSPI controller also uses a programmable sequence engine to provide
flexibility to support existing and future memory devices. It supports
single, dual, quad, octal modes of operation.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Alice Guo <alice.guo@nxp.com>
spi: designware: Allow disabling designware driver in SPL 2025-12-17T10:50:31+00:00 Ralph Siemsen ralph.siemsen@linaro.org 2025-12-11T16:05:23+00:00 136d750c2ed00e11d1acf571fe59f7f4d389f826 To reduce SPL size, make it possible to exclude designware driver, while keeping it enabled in the main u-boot. Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org> Reviewed-by: Sean Anderson <sean.anderson@seco.com> 
To reduce SPL size, make it possible to exclude designware driver,
while keeping it enabled in the main u-boot.

Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
Reviewed-by: Sean Anderson <sean.anderson@seco.com>
spi: cadence: Add driver for xSPI 2025-12-01T05:57:32+00:00 Boon Khai Ng boon.khai.ng@altera.com 2025-10-27T06:36:54+00:00 5eb14e1ea26c22c8994ef6a5013e26eef825c23a This patch ports the Cadence xSPI controller driver from the Linux kernel. The controller supports three operating modes: 1. ACMD (Auto Command) mode - Includes PIO and CDMA submodes. - CDMA mode uses linked descriptors for high-performance, low-overhead operation. - PIO mode is suitable for simple, single-command transactions. 2. STIG (Software Triggered Instruction Generator) mode - Issues low-level 128-bit instructions to memory. - Uses the Slave DMA interface for data transfers. 3. Direct mode - Enables direct data access through the slave interface without commands. Currently, only the STIG work mode is enabled. Additional modes will be supported in future updates. At the same time, also enabling the kconfig option for xSPI driver. This driver has been ported and functionally verified on the Intel Simics platform. It is intended for evaluation and experimental use at this stage. Link: https://lore.kernel.org/all/1632038734-23999-1-git-send-email-pthombar@cadence.com/ Signed-off-by: Boon Khai Ng <boon.khai.ng@altera.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com> 
This patch ports the Cadence xSPI controller driver from
the Linux kernel. The controller supports three operating modes:

1. ACMD (Auto Command) mode
   - Includes PIO and CDMA submodes.
   - CDMA mode uses linked descriptors for high-performance,
     low-overhead operation.
   - PIO mode is suitable for simple, single-command transactions.

2. STIG (Software Triggered Instruction Generator) mode
   - Issues low-level 128-bit instructions to memory.
   - Uses the Slave DMA interface for data transfers.

3. Direct mode
   - Enables direct data access through the slave interface
     without commands.

Currently, only the STIG work mode is enabled. Additional modes will be
supported in future updates.

At the same time, also enabling the kconfig option for xSPI driver.

This driver has been ported and functionally verified on the Intel Simics
platform. It is intended for evaluation and experimental use at this stage.

Link: https://lore.kernel.org/all/1632038734-23999-1-git-send-email-pthombar@cadence.com/

Signed-off-by: Boon Khai Ng <boon.khai.ng@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
spi: Add STM32MP2 Octo-SPI driver support 2025-09-18T15:20:39+00:00 Patrice Chotard patrice.chotard@foss.st.com 2025-09-11T06:59:42+00:00 01eb0a583860aa8bb9960427eac3fbcdbeae1f28 Add STM32 OSPI driver, it supports : - support sNOR / sNAND devices. - Two functional modes: indirect (read/write) and memory-mapped (read). - Single-, dual-, quad-, and octal-SPI communication. - Single data rate (SDR). Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> 
Add STM32 OSPI driver, it supports :
  - support sNOR / sNAND devices.
  - Two functional modes: indirect (read/write) and memory-mapped (read).
  - Single-, dual-, quad-, and octal-SPI communication.
  - Single data rate (SDR).

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
spi: airoha: Add Airoha SPI NAND driver 2025-04-17T13:51:36+00:00 Christian Marangi ansuelsmth@gmail.com 2025-04-07T20:01:56+00:00 6134e4efd432f1be74d48f46d2843bde8a8eb7f3 Add Airoha SPI NAND driver to permit usage of attached SNAND on the Airoha AN7581 SoC. While SPI controller supports DMA transation, due to U-Boot limitation we currently limit it to single command in Manual mode. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> 
Add Airoha SPI NAND driver to permit usage of attached SNAND on the
Airoha AN7581 SoC. While SPI controller supports DMA transation, due to
U-Boot limitation we currently limit it to single command in Manual
mode.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
spi: Add support for ADI SC5XX-family processor SPI peripherals 2025-03-12T16:24:58+00:00 Nathan Barrett-Morrison nathan.morrison@timesys.com 2025-02-26T17:30:33+00:00 7535a9280be1fc81b280517c7c44b5f1c2efc0ba This adds support for the ADI-specific SPI driver present in the ADI SC5xx line of SoCs. This IP block is distinct from the QSPI/OSPI block that uses the Cadence driver. Both may be used at once with appropriate pin muxing configuration. Co-developed-by: Greg Malysa <malysagreg@gmail.com> Signed-off-by: Greg Malysa <malysagreg@gmail.com> Co-developed-by: Angelo Dureghello <angelo.dureghello@timesys.com> Signed-off-by: Angelo Dureghello <angelo.dureghello@timesys.com> Co-developed-by: Ian Roberts <ian.roberts@timesys.com> Signed-off-by: Ian Roberts <ian.roberts@timesys.com> Co-developed-by: Piotr Wojtaszczyk <piotr.wojtaszczyk@timesys.com> Signed-off-by: Piotr Wojtaszczyk <piotr.wojtaszczyk@timesys.com> Signed-off-by: Vasileios Bimpikas <vasileios.bimpikas@analog.com> Signed-off-by: Utsav Agarwal <utsav.agarwal@analog.com> Signed-off-by: Arturs Artamonovs <arturs.artamonovs@analog.com> Signed-off-by: Oliver Gaskell <Oliver.Gaskell@analog.com> Signed-off-by: Nathan Barrett-Morrison <nathan.morrison@timesys.com> 
This adds support for the ADI-specific SPI driver present in the ADI
SC5xx line of SoCs. This IP block is distinct from the QSPI/OSPI block
that uses the Cadence driver. Both may be used at once with appropriate
pin muxing configuration.

Co-developed-by: Greg Malysa <malysagreg@gmail.com>
Signed-off-by: Greg Malysa <malysagreg@gmail.com>
Co-developed-by: Angelo Dureghello <angelo.dureghello@timesys.com>
Signed-off-by: Angelo Dureghello <angelo.dureghello@timesys.com>
Co-developed-by: Ian Roberts <ian.roberts@timesys.com>
Signed-off-by: Ian Roberts <ian.roberts@timesys.com>
Co-developed-by: Piotr Wojtaszczyk <piotr.wojtaszczyk@timesys.com>
Signed-off-by: Piotr Wojtaszczyk <piotr.wojtaszczyk@timesys.com>
Signed-off-by: Vasileios Bimpikas <vasileios.bimpikas@analog.com>
Signed-off-by: Utsav Agarwal <utsav.agarwal@analog.com>
Signed-off-by: Arturs Artamonovs <arturs.artamonovs@analog.com>
Signed-off-by: Oliver Gaskell <Oliver.Gaskell@analog.com>
Signed-off-by: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
global: Rename SPL_TPL_ to PHASE_ 2024-10-11T17:44:48+00:00 Simon Glass sjg@chromium.org 2024-09-30T01:49:54+00:00 5c10c8badf8233cac1593cd2bef4d0379ac9e5bd Use PHASE_ as the symbol to select a particular XPL build. This means that SPL_TPL_ is no-longer set. Update the comment in bootstage to refer to this symbol, instead of SPL_ Signed-off-by: Simon Glass <sjg@chromium.org> 
Use PHASE_ as the symbol to select a particular XPL build. This means
that SPL_TPL_ is no-longer set.

Update the comment in bootstage to refer to this symbol, instead of
SPL_

Signed-off-by: Simon Glass <sjg@chromium.org>
spi: cv1800b: Add spi nor flash controller driver for cv1800b SoC 2024-05-01T16:01:18+00:00 Kongyang Liu seashell11234455@gmail.com 2024-04-20T07:08:23+00:00 6c75bea76a76e2fd21f55107e86696321e427a51 Add spi nor flash controller driver for cv1800b SoC Signed-off-by: Kongyang Liu <seashell11234455@gmail.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> 
Add spi nor flash controller driver for cv1800b SoC

Signed-off-by: Kongyang Liu <seashell11234455@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
spi: add support for Amlogic A1 SPI Flash Controller 2023-10-27T16:49:52+00:00 Igor Prusov IVPrusov@sberdevices.ru 2023-10-24T22:51:39+00:00 b59b0ce118667b6f3c30b848edfe9d1ead89ec8e Add A1 SPIFC driver from Linux. Slightly modified to use u-boot driver framework and accommodate to lack of ioread32_rep/iowrite32_rep. Based on Linux version 6.6-rc4 Signed-off-by: Igor Prusov <IVPrusov@sberdevices.ru> Signed-off-by: Martin Kurbanov <mmkurbanov@sberdevices.ru> Reviewed-by: Simon Glass <sjg@chromium.org> Link: https://lore.kernel.org/r/20231024225140.366571-2-ivprusov@sberdevices.ru Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> [trini: Drop <common.h> as it's not needed] 
Add A1 SPIFC driver from Linux. Slightly modified to use u-boot driver
framework and accommodate to lack of ioread32_rep/iowrite32_rep.

Based on Linux version 6.6-rc4

Signed-off-by: Igor Prusov <IVPrusov@sberdevices.ru>
Signed-off-by: Martin Kurbanov <mmkurbanov@sberdevices.ru>
Reviewed-by: Simon Glass <sjg@chromium.org>
Link: https://lore.kernel.org/r/20231024225140.366571-2-ivprusov@sberdevices.ru
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
[trini: Drop <common.h> as it's not needed]
spi: bcmbca-hsspi: Add driver for newer HSSPI controller 2023-07-13T08:29:57+00:00 William Zhang william.zhang@broadcom.com 2023-06-07T23:37:05+00:00 55c0144bd30dbbb9a3b1cb6987040022756368f2 The newer BCMBCA SoCs such as BCM6756, BCM4912 and BCM6855 include an updated SPI controller that add the capability to allow the driver to control chip select explicitly. Driver can control and keep cs low between the transfers natively. Hence the dummy cs workaround or prepend mode found in the bcm63xx-hsspi driver are no longer needed and this new driver is much cleaner. Port from linux patch: Link: https://lore.kernel.org/r/20230209200246.141520-15-william.zhang@broadcom.com Signed-off-by: William Zhang <william.zhang@broadcom.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> 
The newer BCMBCA SoCs such as BCM6756, BCM4912 and BCM6855 include an
updated SPI controller that add the capability to allow the driver to
control chip select explicitly. Driver can control and keep cs low
between the transfers natively. Hence the dummy cs workaround or prepend
mode found in the bcm63xx-hsspi driver are no longer needed and this new
driver is much cleaner.

Port from linux patch:
Link: https://lore.kernel.org/r/20230209200246.141520-15-william.zhang@broadcom.com
Signed-off-by: William Zhang <william.zhang@broadcom.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>