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<title>u-boot.git/drivers/spi/Makefile, branch v2013.04</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/spi/Makefile?h=v2013.04</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/drivers/spi/Makefile?h=v2013.04'/>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<updated>2013-03-28T17:50:01Z</updated>
<entry>
<title>Merge branch 'u-boot/master' into 'u-boot-arm/master'</title>
<updated>2013-03-28T17:50:01Z</updated>
<author>
<name>Albert ARIBAUD</name>
<email>albert.u.boot@aribaud.net</email>
</author>
<published>2013-03-28T17:50:01Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=009d75ccc11d27b9a083375a88bb93cb746b4800'/>
<id>urn:sha1:009d75ccc11d27b9a083375a88bb93cb746b4800</id>
<content type='text'>
Conflicts:
	drivers/spi/tegra20_sflash.c
	include/fdtdec.h
	lib/fdtdec.c
</content>
</entry>
<entry>
<title>tegra114: add SPI driver</title>
<updated>2013-03-25T16:56:07Z</updated>
<author>
<name>Allen Martin</name>
<email>amartin@nvidia.com</email>
</author>
<published>2013-03-16T18:58:13Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=77c42e80b936cf44334a59a7890c775712f5b707'/>
<id>urn:sha1:77c42e80b936cf44334a59a7890c775712f5b707</id>
<content type='text'>
Add driver for tegra114 SPI controller.  This controller is not
compatible with either the tegra20 or tegra30 controllers, so it
requires a new driver.

Signed-off-by: Allen Martin &lt;amartin@nvidia.com&gt;
Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
Reviewed-by: Stephen Warren &lt;swarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>spi: add common fdt SPI driver interface</title>
<updated>2013-03-25T16:56:06Z</updated>
<author>
<name>Allen Martin</name>
<email>amartin@nvidia.com</email>
</author>
<published>2013-03-16T18:58:07Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=78f47b7353ebe1f243203dcc1ce0a2a374c08a40'/>
<id>urn:sha1:78f47b7353ebe1f243203dcc1ce0a2a374c08a40</id>
<content type='text'>
Add a common interface to fdt based SPI drivers.  Each driver is
represented by a table entry in fdt_spi_drivers[].  If there are
multiple SPI drivers in the table, the first driver to return success
from spi_init() will be registered as the SPI driver.

Signed-off-by: Allen Martin &lt;amartin@nvidia.com&gt;
Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
Reviewed-by: Stephen Warren &lt;swarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>tegra: spi: rename tegra SPI drivers</title>
<updated>2013-03-25T16:56:05Z</updated>
<author>
<name>Allen Martin</name>
<email>amartin@nvidia.com</email>
</author>
<published>2013-03-16T18:58:03Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=ff1da6fb5fe50ac15dd988e81a782a4599102424'/>
<id>urn:sha1:ff1da6fb5fe50ac15dd988e81a782a4599102424</id>
<content type='text'>
Rename tegra SPI drivers to tegra20_flash and tegra20_slink in
preparation for commonization and addition of tegra114_spi.

Signed-off-by: Allen Martin &lt;amartin@nvidia.com&gt;
Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
Reviewed-by: Stephen Warren &lt;swarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>x86: spi: Add Intel ICH driver</title>
<updated>2013-03-19T15:45:36Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2013-03-19T04:58:56Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=1853030e2164c849c09f1ba051d243265e2591ec'/>
<id>urn:sha1:1853030e2164c849c09f1ba051d243265e2591ec</id>
<content type='text'>
This supports Intel ICH7/9. The Intel controller is a little unusual in
that it is mostly intended for use with SPI flash, and has some
optimisations and features specifically for that application. In
particular it is not possible to support ongoing transactions that
continue over many calls with SPI_XFER_BEGIN and SPI_XFER_END.

This driver supports writes of up to 64 bytes at a time, the limit
for the controller. Future work will improve this.

Signed-off-by: Bernie Thompson &lt;bhthompson@chromium.org&gt;
Signed-off-by: Duncan Laurie &lt;dlaurie@chromium.org&gt;
Signed-off-by: Bill Richardson &lt;wfrichar@chromium.org&gt;
Signed-off-by: Vadim Bendebury &lt;vbendeb@chromium.org&gt;
Signed-off-by: Gabe Black &lt;gabeblack@chromium.org&gt;
Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>spi: Add function to allocate a new SPI slave</title>
<updated>2013-03-19T15:45:36Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2013-03-11T06:08:00Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=ba6c3ce9bd0ac572592dc909878117dce219c564'/>
<id>urn:sha1:ba6c3ce9bd0ac572592dc909878117dce219c564</id>
<content type='text'>
At present it is difficult to extend the SPI structure since all
drivers allocate it themselves, and few of them zero all fields. Add
a new function spi_alloc_slave() which can be used by SPI drivers
to perform this allocation, and thus ensure that all drivers can
better cope with SPI structure changes.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>blackfin: add bf6xx spi driver</title>
<updated>2013-03-04T05:42:07Z</updated>
<author>
<name>Scott Jiang</name>
<email>scott.jiang.linux@gmail.com</email>
</author>
<published>2011-11-29T23:03:26Z</published>
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<id>urn:sha1:4a207e8b9a1ecc3e87d5a63bb5442dbcd50bd4b6</id>
<content type='text'>
Spi driver for bf60x is different from old one, so implement a new
driver for it.

Signed-off-by: Scott Jiang &lt;scott.jiang.linux@gmail.com&gt;
Signed-off-by: Sonic Zhang &lt;sonic.zhang@analog.com&gt;
Signed-off-by: Bob Liu &lt;lliubbo@gmail.com&gt;
Signed-off-by: Sonic Zhang &lt;sonic.adi@gmail.com&gt;
</content>
</entry>
<entry>
<title>tegra: add SPI SLINK driver</title>
<updated>2013-02-11T17:35:25Z</updated>
<author>
<name>Allen Martin</name>
<email>amartin@nvidia.com</email>
</author>
<published>2013-01-29T13:51:28Z</published>
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<id>urn:sha1:b19f57491a39542c9916367a9041199cb547d0e8</id>
<content type='text'>
Add driver for tegra SPI "SLINK" style driver.  This controller is
similar to the tegra20 SPI "SFLASH" controller.  The difference is
that the SLINK controller is a genernal purpose SPI controller and the
SFLASH controller is special purpose and can only talk to FLASH
devices.  In addition there are potentially many instances of an SLINK
controller on tegra and only a single instance of SFLASH.  Tegra20 is
currently ths only version of tegra that instantiates an SFLASH
controller.

This driver supports basic PIO mode of operation and is configurable
(CONFIG_OF_CONTROL) to be driven off devicetree bindings.  Up to 4
devices per controller may be attached, although typically only a
single chip select line is exposed from tegra per controller so in
reality this is usually limited to 1.

To enable this driver, use CONFIG_TEGRA_SLINK

Signed-off-by: Allen Martin &lt;amartin@nvidia.com&gt;
Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>SPI: Add SPI Driver for EXYNOS.</title>
<updated>2012-11-15T12:08:21Z</updated>
<author>
<name>Rajeshwari Shinde</name>
<email>rajeshwari.s@samsung.com</email>
</author>
<published>2012-11-02T01:15:36Z</published>
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<id>urn:sha1:1bf43b829eae86e70895fb90f0b3a102dfc7ba2c</id>
<content type='text'>
This patch adds SPI driver for EXYNOS.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Padmavathi Venna &lt;padma.v@samsung.com&gt;
Signed-off-by: Gabe Black &lt;gabeblack@google.com&gt;
Signed-off-by: Rajeshwari Shinde &lt;rajeshwari.s@samsung.com&gt;
Signed-off-by: Hatim Ali &lt;hatim.rv@samsung.com&gt;
Acked-by: Mike Frysinger &lt;vapier@gentoo.org&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
Tested-by: jy0922.shim@samsung.com
Signed-off-by: Minkyu Kang &lt;mk7.kang@samsung.com&gt;
</content>
</entry>
<entry>
<title>ColdFire: Queued SPI driver</title>
<updated>2012-09-20T12:39:27Z</updated>
<author>
<name>Richard Retanubun</name>
<email>RichardRetanubun@RuggedCom.com</email>
</author>
<published>2011-03-24T08:58:11Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=59d0612252a0ffcb878a1891249d32a306a24fa6'/>
<id>urn:sha1:59d0612252a0ffcb878a1891249d32a306a24fa6</id>
<content type='text'>
This patch adds a driver for Freescale Colfire Queued SPI bus.
Coded to work with 8 bits per transfer to use with SPI flash.
CPOL, CPHA, and CS_ACTIVE_HIGH can be configured.

Tested with MCF5270 which have 4 chip selects.

Activate by #define CONFIG_CF_QSPI in board config.

Signed-off-by: Richard Retanubun &lt;richardretanubun@ruggedcom.com&gt;
</content>
</entry>
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