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<title>u-boot.git/drivers/spi/Makefile, branch v2018.11</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/spi/Makefile?h=v2018.11</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/drivers/spi/Makefile?h=v2018.11'/>
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<updated>2018-10-04T12:57:28Z</updated>
<entry>
<title>spi: Add SPI driver for MT76xx SoCs</title>
<updated>2018-10-04T12:57:28Z</updated>
<author>
<name>Stefan Roese</name>
<email>sr@denx.de</email>
</author>
<published>2018-08-16T08:48:48Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=5eee9dee419f940ea75977df8b7ed8bb12bc029f'/>
<id>urn:sha1:5eee9dee419f940ea75977df8b7ed8bb12bc029f</id>
<content type='text'>
This patch adds the SPI driver for the MediaTek MT7688 SoC (and
derivates). Its been tested on the LinkIt Smart 7688 and the Gardena
Smart Gateway with and SPI NOR on CS0 and on the Gardena Smart
Gateway additionally with an SPI NAND on CS1.

Note that the SPI controller only supports a max transfer size of 32
bytes. This driver implementes a workaround to enable bigger xfer
sizes to speed up the transfer especially for the SPI NAND support.

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
Cc: Jagan Teki &lt;jagan@openedev.com&gt;
Cc: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
Cc: Piotr Dymacz &lt;pepe2k@gmail.com&gt;
Reviewed-by: Jagan Teki &lt;jagan@openedev.com&gt;
Reviewed-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
</content>
</entry>
<entry>
<title>Merge branch 'master' of git://git.denx.de/u-boot-spi</title>
<updated>2018-10-02T21:01:46Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2018-10-02T17:02:22Z</published>
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<id>urn:sha1:592cd5defd4f71d34ffcbd8dd3326bc10f662e20</id>
<content type='text'>
This is the PR for SPI-NAND changes along with few spi changes.

[trini: Re-sync changes for ls1012afrwy_qspi*_defconfig]
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>spi: add support for ARM PL022 SPI controller</title>
<updated>2018-09-26T01:49:18Z</updated>
<author>
<name>Quentin Schulz</name>
<email>quentin.schulz@bootlin.com</email>
</author>
<published>2018-08-31T14:28:29Z</published>
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<id>urn:sha1:8a4791fa08fb456f9cf8ef95083ddd4e0d07b48e</id>
<content type='text'>
This adds support for the ARM PL022 SPI controller for the standard
variant (0x00041022) which has a 16bit wide and 8 locations deep TX/RX
FIFO.

A few parts were borrowed from the Linux kernel driver.

Cc: Armando Visconti &lt;armando.visconti@st.com&gt;
Cc: Vipin Kumar &lt;vipin.kumar@st.com&gt;
Signed-off-by: Quentin Schulz &lt;quentin.schulz@bootlin.com&gt;
</content>
</entry>
<entry>
<title>spi: Extend the core to ease integration of SPI memory controllers</title>
<updated>2018-09-20T14:40:49Z</updated>
<author>
<name>Boris Brezillon</name>
<email>boris.brezillon@bootlin.com</email>
</author>
<published>2018-08-16T15:30:11Z</published>
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<id>urn:sha1:d13f5b254a43e292814a618f60a2696ba01267a7</id>
<content type='text'>
Some controllers are exposing high-level interfaces to access various
kind of SPI memories. Unfortunately they do not fit in the current
spi_controller model and usually have drivers placed in
drivers/mtd/spi-nor which are only supporting SPI NORs and not SPI
memories in general.

This is an attempt at defining a SPI memory interface which works for
all kinds of SPI memories (NORs, NANDs, SRAMs).

Signed-off-by: Boris Brezillon &lt;boris.brezillon@bootlin.com&gt;
Signed-off-by: Miquel Raynal &lt;miquel.raynal@bootlin.com&gt;
Acked-by: Jagan Teki &lt;jagan@openedev.com&gt;
</content>
</entry>
<entry>
<title>arm: sunxi: Allwinner A10 SPI driver</title>
<updated>2018-08-03T05:44:08Z</updated>
<author>
<name>Stefan Mavrodiev</name>
<email>stefan@olimex.com</email>
</author>
<published>2018-02-06T13:14:33Z</published>
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<id>urn:sha1:7f25d8179776226a8ecfbaad3d3a88e9acd89f28</id>
<content type='text'>
Add spi driver for sun4i, sun5i and sun7i SoCs. The driver is
adapted from mailine kernel.

Signed-off-by: Stefan Mavrodiev &lt;stefan@olimex.com&gt;
Reviewed-by: Jagan Teki &lt;jagan@openedev.com&gt;
</content>
</entry>
<entry>
<title>spi: zynqmp_gqspi: Add support for ZynqMP qspi driver</title>
<updated>2018-07-16T08:31:47Z</updated>
<author>
<name>Siva Durga Prasad Paladugu</name>
<email>siva.durga.paladugu@xilinx.com</email>
</author>
<published>2018-07-04T12:01:23Z</published>
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<id>urn:sha1:22cca1730ec42b84f23173a6075ffa39a9a77bdc</id>
<content type='text'>
This patch adds qspi driver support for ZynqMP SoC. This
driver is responsible for communicating with qspi flash
devices.

Signed-off-by: Siva Durga Prasad Paladugu &lt;siva.durga.paladugu@xilinx.com&gt;
[jagan: removed GQSPI_MIO_NUM_ macros]
Reviewed-by: Jagan Teki &lt;jagan@openedev.com&gt;
</content>
</entry>
<entry>
<title>board: arm: Add support for Broadcom BCM7445</title>
<updated>2018-07-10T20:55:57Z</updated>
<author>
<name>Thomas Fitzsimmons</name>
<email>fitzsim@fitzsim.org</email>
</author>
<published>2018-06-08T21:59:45Z</published>
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<id>urn:sha1:894c3ad27fa940beb7fdc07d01dcfe81c03d0481</id>
<content type='text'>
Add support for loading U-Boot on the Broadcom 7445 SoC.  This port
assumes Broadcom's BOLT bootloader is acting as the second stage
bootloader, and U-Boot is acting as the third stage bootloader, loaded
as an ELF program by BOLT.

Signed-off-by: Thomas Fitzsimmons &lt;fitzsim@fitzsim.org&gt;
Cc: Stefan Roese &lt;sr@denx.de&gt;
Cc: Tom Rini &lt;trini@konsulko.com&gt;
Cc: Florian Fainelli &lt;f.fainelli@gmail.com&gt;
</content>
</entry>
<entry>
<title>SPDX: Convert all of our single license tags to Linux Kernel style</title>
<updated>2018-05-07T13:34:12Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2018-05-06T21:58:06Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=83d290c56fab2d38cd1ab4c4cc7099559c1d5046'/>
<id>urn:sha1:83d290c56fab2d38cd1ab4c4cc7099559c1d5046</id>
<content type='text'>
When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from.  So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry.  Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.

In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.

This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents.  There's also a few places where I found we did not have a tag
and have introduced one.

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>mtd: spi: Add Renesas RPC SPI-flash driver</title>
<updated>2018-04-11T21:12:01Z</updated>
<author>
<name>Marek Vasut</name>
<email>marek.vasut+renesas@gmail.com</email>
</author>
<published>2017-11-29T05:29:46Z</published>
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<id>urn:sha1:fbebea27e16eb760f1f2109a7535003bf359ba2b</id>
<content type='text'>
Add driver for the RPC block in SPI-flash mode. This driver allows
access to a SPI NOR flash attached to the RPC block and does not
support RPC in Hyperflash mode. Note that this block is extremely
selective when communicating with the SPI NOR.

Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@gmail.com&gt;
Cc: Nobuhiro Iwamatsu &lt;iwamatsu@nigauri.org&gt;
</content>
</entry>
<entry>
<title>dm: spi: add BCM63xx HSSPI driver</title>
<updated>2018-01-24T06:34:06Z</updated>
<author>
<name>Álvaro Fernández Rojas</name>
<email>noltari@gmail.com</email>
</author>
<published>2018-01-20T01:13:38Z</published>
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<id>urn:sha1:29cc4368ad4b8d67ae457681e9249e2008d6fee5</id>
<content type='text'>
This driver is a simplified version of linux/drivers/spi/spi-bcm63xx-hsspi.c

Signed-off-by: Álvaro Fernández Rojas &lt;noltari@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
Reviewed-by: Jagan Teki &lt;jagan@openedev.com&gt;
</content>
</entry>
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