u-boot.git/drivers/spi/Makefile, branch v2022.07

spi: npcm-fiu: add NPCM7xx FIU controller driver

2022-05-03T12:19:48Z

Add Nuvoton NPCM BMC Flash Interface Unit(FIU) SPI master controller driver using SPI-MEM interface. The FIU supports single, dual or quad communication interface. The FIU controller driver provides flash access in UMA(User Mode Access) mode by using an indirect address/data mechanism. the dts node is followed upstream kernel dts name. Signed-off-by: Jim Liu Signed-off-by: Stanley Chu Reviewed-by: Jagan Teki [Jagan: fixed the Kconfig, Makefile order] Signed-off-by: Jagan Teki

driver: spi: add bcm iproc qspi support

2022-02-24T08:12:50Z

IPROC qspi driver supports both BSPI and MSPI modes. Signed-off-by: Rayagonda Kokatanur Signed-off-by: Bharat Gooty Acked-by: Rayagonda Kokatanur Signed-off-by: Roman Bacik Reviewed-by: Jagan Teki

spi: apple: Add driver for Apple SPI controller

2022-02-10T21:44:23Z

Add a driver for the SPI controller integrated on Apple SoCs. This is necessary to support the keyboard on Apple Silicon laopts since their keyboard uses an Apple-specific HID over SPI protocol. Signed-off-by: Mark Kettenis Reviewed-by: Simon Glass Tested on: Macbook Air M1 Tested-by: Simon Glass

spi: rockchip_sfc: add support for Rockchip SFC

2021-08-12T01:34:11Z

This patch adds support for the Rockchip serial flash controller found on the PX30 SoC. It should work for versions 3-5 of the SFC IP, however I am only able to test it on v3. This is adapted from the WIP SPI-MEM driver for the SFC on mainline Linux. Note that the main difference between this and earlier versions of the driver is that this one does not support DMA. In testing the performance difference (performing a dual mode read on a 128Mb chip) is negligible. DMA, if used, must also be disabled in SPL mode when using A-TF anyway. Signed-off-by: Chris Morgan Signed-off-by: Jon Lin Reviewed-by: Kever Yang

spi: fsl_qspi: Build driver only if DM_SPI is available

2021-07-10T14:53:34Z

The driver depends on DM_SPI and if it's not available (e. g. in SPL), then we should not try to build it as this will fail. Signed-off-by: Frieder Schrempf

spi: synquacer: Add HSSPI SPI controller driver for SynQuacer

2021-07-06T18:07:36Z

This is a driver for the HSSPI SPI controller on SynQuacer SoC. The HSSPI has command sequence mode (memory mapped) and direct mode (FIFO access). The driver will operate it under the direct mode. And before booting OS, it switch back to the command sequence mode since that is compatible with default EDK2 behavior. Signed-off-by: Jassi Brar Signed-off-by: Masami Hiramatsu

spi: Add MXIC controller driver

2021-06-25T15:29:45Z

Add a driver for Macronix SPI controller IP. This patch referred from linux spi-mxic.c. The difference from the linux version is described here. 1. To adapt uboot spi framework, modify some functions naming. 2. Remove the incompatible functions of Uboot. 3. Add dummy byte recalculattion function to support dummy buswidth not align data buswidth operation.(ex: 1-1-4, 1-1-8) 4. Add Octal mode support. Signed-off-by: Zhengxun Reviewed-by: Jagan Teki [jagan: fixed file permission, comment line, kconfig] Signed-off-by: Jagan Teki

spi: mtk_snor: add support for MTK SPI NOR controller

2021-01-29T15:35:14Z

This patch adds support for MTK SPI NOR controller, which you can see on mt7622 & mt7629. 1. This controller is designed only for SPI NOR. We can't adjust its bus clock dynamically. Set clock in dts instead. 2. This controller only supports 1-1-1 write mode. 3. Remove mtk_snor_match_read() since upper SPI-MEM layer already handles command. 4. sf read/write/update commands are tested with this driver. Signed-off-by: SkyLake.Huang

spi: add spi controller support for MediaTek MT7620 SoC

2021-01-24T20:39:26Z

This patch adds spi controller support for MediaTek MT7620 SoC. The SPI controller supports two chip selects. These two chip selects are implemented as two separate register groups, but they share the same bus (DI/DO/CLK), only CS pins are dedicated for each register group. Appearently these two register groups cannot operates simulataneously so they are implemented as one controller. Reviewed-by: Stefan Roese Signed-off-by: Weijie Gao

spi: ca_sflash: Add CAxxxx SPI Flash Controller

2020-12-18T10:46:37Z

Add SPI Flash controller driver for Cortina Access CAxxxx SoCs Signed-off-by: Pengpeng Chen Signed-off-by: Alex Nemirovsky CC: Vignesh R CC: Tom Rini [jagan: rebase on master] Signed-off-by: Jagan Teki Reviewed-by: Jagan Teki