u-boot.git/drivers/spi/Makefile, branch v2025.01

global: Rename SPL_TPL_ to PHASE_

2024-10-11T17:44:48Z

Use PHASE_ as the symbol to select a particular XPL build. This means that SPL_TPL_ is no-longer set. Update the comment in bootstage to refer to this symbol, instead of SPL_ Signed-off-by: Simon Glass

spi: cv1800b: Add spi nor flash controller driver for cv1800b SoC

2024-05-01T16:01:18Z

Add spi nor flash controller driver for cv1800b SoC Signed-off-by: Kongyang Liu Reviewed-by: Leo Yu-Chi Liang

spi: add support for Amlogic A1 SPI Flash Controller

2023-10-27T16:49:52Z

Add A1 SPIFC driver from Linux. Slightly modified to use u-boot driver framework and accommodate to lack of ioread32_rep/iowrite32_rep. Based on Linux version 6.6-rc4 Signed-off-by: Igor Prusov Signed-off-by: Martin Kurbanov Reviewed-by: Simon Glass Link: https://lore.kernel.org/r/20231024225140.366571-2-ivprusov@sberdevices.ru Signed-off-by: Neil Armstrong [trini: Drop as it's not needed]

spi: bcmbca-hsspi: Add driver for newer HSSPI controller

2023-07-13T08:29:57Z

The newer BCMBCA SoCs such as BCM6756, BCM4912 and BCM6855 include an updated SPI controller that add the capability to allow the driver to control chip select explicitly. Driver can control and keep cs low between the transfers natively. Hence the dummy cs workaround or prepend mode found in the bcm63xx-hsspi driver are no longer needed and this new driver is much cleaner. Port from linux patch: Link: https://lore.kernel.org/r/20230209200246.141520-15-william.zhang@broadcom.com Signed-off-by: William Zhang Reviewed-by: Jagan Teki

spi: Add Socionext F_OSPI SPI flash controller driver

2023-01-26T15:23:20Z

Introduce Socionext F_OSPI controller driver. This controller is used to communicate with slave devices such as SPI flash memories. It supports 4 slave devices and up to 8-bit wide bus, but supports master mode only. This driver uses spi-mem framework for SPI flash memory access, and can only operate indirect access mode and single data rate mode. Signed-off-by: Kunihiko Hayashi Reviewed-by: Jagan Teki

Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-riscv

2022-11-03T12:27:44Z

spi: Add Microchip PolarFire SoC QSPI driver

2022-11-03T05:27:56Z

Add QSPI driver code for the Microchip PolarFire SoC. This driver supports the QSPI standard, dual and quad mode interfaces. Co-developed-by: Naga Sureshkumar Relli Signed-off-by: Naga Sureshkumar Relli Signed-off-by: Padmarao Begari Reviewed-by: Conor Dooley

spi: nuvoton: add NPCM PSPI controller driver

2022-10-27T07:11:36Z

Add Nuvoton NPCM BMC Peripheral SPI controller driver. NPCM750 include two general-purpose SPI interface. Signed-off-by: Jim Liu Reviewed-by: Jagan Teki

spi: add support for MediaTek spi-mem controller

2022-09-23T19:09:15Z

This patch adds support for spi-mem controller found on newer MediaTek SoCs This controller supports Single/Dual/Quad SPI mode. Reviewed-by: Simon Glass Tested-by: Daniel Golle Signed-off-by: SkyLake.Huang

spi: aspeed: Add ASPEED SPI controller driver

2022-09-13T16:08:40Z

Add ASPEED BMC FMC/SPI memory controller driver with spi-mem interface for AST2500 and AST2600 platform. There are three SPI memory controllers embedded in an ASPEED SoC. - FMC: Named as Firmware Memory Controller. After AC on, MCU ROM fetches initial device boot image from FMC chip select(CS) 0. - SPI1: Play the role of a SPI Master controller. Or, there is a dedicated path for HOST(X86) to access its BIOS flash mounted under BMC. spi-aspeed-smc.c implements the control sequence when SPI1 is a SPI master. - SPI2: It is a pure SPI flash controller. For most scenarios, flashes mounted under it are for pure storage purpose. ASPEED SPI controller supports 1-1-1, 1-1-2 and 1-1-4 SPI flash mode. Three types of command mode are supported, normal mode, command read/write mode and user mode. - Normal mode: Default mode. After power on, normal read command 03h or 13h is used to fetch boot image from SPI flash. - AST2500: Only 03h command can be used after power on or reset. - AST2600: If FMC04[6:4] is set, 13h command is used, otherwise, 03h command. The address length is decided by FMC04[2:0]. - Command mode: SPI controller can send command and address automatically when CPU read/write the related remapped or decoded address area. The command used by this mode can be configured by FMC10/14/18[23:16]. Also, the address length is decided by FMC04[2:0]. This mode will be implemented in the following patch series. - User mode: It is a traditional and pure SPI operation, where SPI transmission is controlled by CPU. It is the main mode in this patch. Each SPI controller in ASPEED SoC has its own decoded address mapping. Within each SPI controller decoded address, driver can assign a specific address region for each CS of a SPI controller. The decoded address cannot overlap to each other. With normal mode and command mode, the decoded address accessed by the CPU determines which CS is active. When user mode is adopted, the CS decoded address is a FIFO, CPU can send/receive any SPI transmission by accessing the related decoded address for the target CS. This patch only implements user mode initially. Command read/write mode will be implemented in the following patches. Signed-off-by: Chin-Ting Kuo