u-boot.git/drivers/spi, branch main

fix non-existing sysam.it domain

2026-08-28T18:18:11Z

Change "Angelo Dureghello" emails replacing non-existing domain with the currently working one. Signed-off-by: Angelo Dureghello Acked-by: Michal Simek

spi: zynqmp_gqspi: fix quad mode bus conflict

2026-08-12T04:54:37Z

Starting the GENFIFO after each CMD and ADDR entry creates a gap between the address phase (TX) and data phase (RX). For read commands without dummy cycles, the controller is still driving DQ2/DQ3 HIGH when the flash switches to output mode, causing a bus conflict. Split the GENFIFO helper into a write-only variant and a start-and-wait variant. Queue CMD, ADDR and dummy entries without starting the GENFIFO. The data phase appends its entry and starts the queued sequence, keeping the address-to-data transition continuous. Since genfifo_cmd() no longer triggers after each entry, operations without a data phase have no trigger path. Call start_gen_fifo() from exec_op() before deasserting chip select to execute the queued CMD and ADDR entries. Fixes: 22cca1730ec4 ("spi: zynqmp_gqspi: Add support for ZynqMP qspi driver") Signed-off-by: Suraj Kakade Signed-off-by: Padmarao Begari Signed-off-by: Michal Simek Link: https://patch.msgid.link/20260709083757.1851446-1-suraj.hanumantkakade@amd.com

mtd: spi: renesas: Add R-Car Gen5 DT compatible

2026-08-07T19:58:59Z

Add device tree compatible string "renesas,rcar-gen5-rpc-if" to the driver to match on upstream RPC DT node in R-Car Gen5 DTs. Signed-off-by: Marek Vasut

mtd: spi: renesas: Align macro prefixes

2026-08-07T19:58:59Z

Remove the IF from RPCIF to align the register macros with each other. No functional change. Fixes: d5162463243d ("mtd: spi: renesas: Configure RPC PHY timing registers") Signed-off-by: Marek Vasut

spi: sunxi: add support for A523 SPI controller

2026-07-26T21:20:07Z

The SPI controllers in the Allwinner A523/A527/T527 SoCs is very close to the one used in the R329 and D1 generation, definitely as far as our driver is concerned. Add the new compatible string, but use the existing config section from the previous SoC generation. Signed-off-by: Andre Przywara Acked-by: Jernej Skrabec

Merge tag 'riscv-for-v2026.10-rc1' of https://git.u-boot-project.org/u-boot/custodians/u-boot-riscv

2026-07-21T15:06:07Z

CI: https://git.u-boot-project.org/u-boot/custodians/u-boot-riscv/-/pipelines/676 - Adds support for the SpacemiT K1 and - Updates the MAINTAINERS.

spi: fsl: add support for Spacemit K1 SoC

2026-07-21T09:16:01Z

Make FSL QSPI driver supporting Spacemit K1 SoC. Signed-off-by: Raymond Mao Signed-off-by: Guodong Xu

spi: dw: Allow bits_per_word to be configured by device drivers

2026-07-20T19:16:10Z

The DesignWare SPI controller supports configurable bits_per_word (typically 4-32 bits), but this was previously hardcoded to 8 bits in the driver initialization. This patch enables bits_per_word to be set dynamically by upper-level device drivers, matching the approach used in Linux. The controller reads the bits_per_word value from the spi_slave structure during each transfer, allowing different SPI devices on the same bus to use different word sizes. Implementation details: - Read slave->bits_per_word in dw_spi_xfer() before each transfer - Validate requested value against controller capabilities (4 to max_xfer) - Default to 8 bits if not set (maintains backward compatibility) This follows the Linux model where spi_device drivers set bits_per_word, and the controller driver reads it in the transfer function. Device drivers can now set slave->bits_per_word before calling spi_xfer(). Example usage in device driver: slave->bits_per_word = 16; spi_xfer(slave, ...); Backward compatible: Existing drivers that don't set bits_per_word will continue to work with the default 8-bit transfers. Signed-off-by: Boon Khai Ng

treewide: Kconfig: use bool instead of tristate

2026-07-10T21:45:57Z

U-Boot does not support modules, so having tristate options is useless. Therefore this patch does a blind replace of all tristate options to bool tree-wide. Signed-off-by: Anshul Dalal Reviewed-by: Heiko Schocher Reviewed-by: Quentin Schulz Reviewed-by: Siddharth Vadapalli Reviewed-by: Neha Malcom Francis Reviewed-by: Romain Gantois Reviewed-by: Simon Glass

Merge patch series "arm: aspeed: add initial AST2700 SoC support"

2026-06-29T21:29:56Z

Ryan Chen says: AST2700 is the 8th generation of Integrated Remote Management Processor introduced by ASPEED Technology Inc. It is a Board Management Controller (BMC) SoC family with a dual-die architecture: SoC0 ("CPU" die with four ARM Cortex-A35 application cores) and SoC1 ("IO" die with peripherals) each SoC have its own SCU PLLs, clock dividers and reset domains. Link: https://lore.kernel.org/r/20260612-ast2700_clk-v4-0-9bea29cfdc39@aspeedtech.com