u-boot.git/drivers/spi, branch next

Merge tag 'u-boot-rockchip-2027.01-20260828' of https://git.u-boot-project.org/u-boot/custodians/u-boot-rockchip into next

2026-08-29T15:56:00Z

- Fixed possible SPI hangs when only PICO is routed (TX-only), - Added support for ROC-RK3399-PC-PLUS (via roc-pc-rk3399_defconfig)

Merge tag 'mediatek-for-next-2026-08-24' of https://git.u-boot-project.org/u-boot/custodians/u-boot-mediatek into next

2026-08-25T17:36:46Z

* New HDMI PHY and I2C DDC drivers, default EDID_ADDR macro * MT8189 clock qualifier fix * Phase-aware PSCI reset (MT8195/MT8365) * dwc_eth_qos MT8366 support * MediaTek TPHY v3 hardware support * mtk_snor mt8188/mt8189 compatible-string cleanup * MT6358/MT6366 PMIC regulator + pwrap support * MediaTek pinctrl Kconfig cleanup (per-SoC symbols → single driver + TARGET_*) * New MT8366 pinctrl driver + dt-bindings header * MediaTek serial driver clock-handling fixes

spi: mtk_snor: combine mt8188 and mt8189 into mediatek,mt8186-nor

2026-08-24T23:11:10Z

Replace "mediatek,mt8188-nor" and "mediatek,mt8189-nor" with "mediatek,mt8186-nor" in the mtk_snor driver. Both of these have "mediatek,mt8186-nor" as a fallback, so we can use that instead of adding each new compatible when we add more similar SoCs. Reviewed-by: Julien Stephan Link: https://patch.msgid.link/20260806-mtk-snor-fallback-compatible-v1-1-74559b491b4a@baylibre.com Signed-off-by: David Lechner

spi: rockchip: skip the unused FIFO direction on a one-wire device

2026-08-24T08:53:00Z

The controller has a transfer-mode field that can run transmit-only or receive-only instead of both, which leaves the unused FIFO out of the transfer entirely. The driver never used it for that: claim_bus always programmed TMOD_TR, and the only other mode came from an opportunistic switch to TMOD_RO for read-only transfers. A device described with spi-{tx,rx}-bus-width = <0> has no wire in that direction at all, so now that the width reaches plat->mode as SPI_NO_TX/SPI_NO_RX, pick the transfer mode from it. A write-only display stops clocking receive bytes nobody reads. The transmit-only case needs one more change. The 8-bit loop paces itself on the receive FIFO and sets toread unconditionally, so with no receive path it would wait on a FIFO that stays empty forever. Leave toread at zero there and let the existing wait_till_not_busy() at the end of the chunk handle completion, which is the same thing that already covers a transmit component today. The restore at the end of a read-only transfer went back to a hardcoded TMOD_TR, which would undo the device's own mode. Restore what the mode asks for instead. Signed-off-by: Cole Munz Tested-by: Alexey Charkov Reviewed-by: Quentin Schulz Link: https://patch.msgid.link/3cf8dc75d461caf6076c35275021bbcdc0943de1.1787309754.git.Munzzyy1@proton.me Signed-off-by: Quentin Schulz

spi: Handle spi-{tx, rx}-bus-width 0 as SPI_NO_TX/SPI_NO_RX

2026-08-24T08:53:00Z

The spi-peripheral-props binding shipped in dts/upstream allows a bus width of 0, meaning no RX or TX is possible on this device. The switches in spi_slave_of_to_plat() only handle 1/2/4/8, so a width of 0 falls through to the default case and warns "spi-rx-bus-width 0 not supported" on every boot, even though the devicetree is valid per the binding. The fact that the wire is missing is then dropped from plat->mode. Map 0 to new SPI_NO_TX/SPI_NO_RX mode bits, as Linux has done since v5.12 ("spi: Add SPI_NO_TX/RX support", mainline d962608ce218). Bits 16 and 17 are the first free mode bits. Mapping the bits is not enough on its own, as Quentin pointed out: nothing would stop a caller from asking for a transfer in a direction that has no wire, and every controller driver would need its own guard. Validate centrally in dm_spi_xfer() instead, matching Linux's __spi_validate(): a din on a SPI_NO_RX device or a dout on a SPI_NO_TX device fails with -EINVAL before it reaches the driver. A new sandbox test covers both rejections. This comes up on devices with no MISO line at all, such as a write-only SPI display described with spi-rx-bus-width = <0>. Signed-off-by: Cole Munz Acked-by: Quentin Schulz Link: https://patch.msgid.link/ae6a85d6f985b63c8f5a3fe8deeab89d79757b14.1787309754.git.Munzzyy1@proton.me Signed-off-by: Quentin Schulz

spi: zynqmp_gqspi: fix quad mode bus conflict

2026-08-12T04:54:37Z

Starting the GENFIFO after each CMD and ADDR entry creates a gap between the address phase (TX) and data phase (RX). For read commands without dummy cycles, the controller is still driving DQ2/DQ3 HIGH when the flash switches to output mode, causing a bus conflict. Split the GENFIFO helper into a write-only variant and a start-and-wait variant. Queue CMD, ADDR and dummy entries without starting the GENFIFO. The data phase appends its entry and starts the queued sequence, keeping the address-to-data transition continuous. Since genfifo_cmd() no longer triggers after each entry, operations without a data phase have no trigger path. Call start_gen_fifo() from exec_op() before deasserting chip select to execute the queued CMD and ADDR entries. Fixes: 22cca1730ec4 ("spi: zynqmp_gqspi: Add support for ZynqMP qspi driver") Signed-off-by: Suraj Kakade Signed-off-by: Padmarao Begari Signed-off-by: Michal Simek Link: https://patch.msgid.link/20260709083757.1851446-1-suraj.hanumantkakade@amd.com

mtd: spi: renesas: Add R-Car Gen5 DT compatible

2026-08-07T19:58:59Z

Add device tree compatible string "renesas,rcar-gen5-rpc-if" to the driver to match on upstream RPC DT node in R-Car Gen5 DTs. Signed-off-by: Marek Vasut

mtd: spi: renesas: Align macro prefixes

2026-08-07T19:58:59Z

Remove the IF from RPCIF to align the register macros with each other. No functional change. Fixes: d5162463243d ("mtd: spi: renesas: Configure RPC PHY timing registers") Signed-off-by: Marek Vasut

spi: sunxi: add support for A523 SPI controller

2026-07-26T21:20:07Z

The SPI controllers in the Allwinner A523/A527/T527 SoCs is very close to the one used in the R329 and D1 generation, definitely as far as our driver is concerned. Add the new compatible string, but use the existing config section from the previous SoC generation. Signed-off-by: Andre Przywara Acked-by: Jernej Skrabec

Merge tag 'riscv-for-v2026.10-rc1' of https://git.u-boot-project.org/u-boot/custodians/u-boot-riscv

2026-07-21T15:06:07Z

CI: https://git.u-boot-project.org/u-boot/custodians/u-boot-riscv/-/pipelines/676 - Adds support for the SpacemiT K1 and - Updates the MAINTAINERS.