u-boot.git/drivers/spi, branch v2012.10

Merge branch 'master' of git://git.denx.de/u-boot-arm

2012-09-21T21:53:13+00:00

Merge remote-tracking branch 'u-boot-imx/master'

2012-09-20T22:26:19+00:00

ColdFire: Queued SPI driver

2012-09-20T12:39:27+00:00

This patch adds a driver for Freescale Colfire Queued SPI bus.
Coded to work with 8 bits per transfer to use with SPI flash.
CPOL, CPHA, and CS_ACTIVE_HIGH can be configured.

Tested with MCF5270 which have 4 chip selects.

Activate by #define CONFIG_CF_QSPI in board config.

Signed-off-by: Richard Retanubun

mpc8xxx_spi: fix SPI support on MPC8308RDB

2012-09-18T21:16:44+00:00

The MPC8308RDB Reference Manual states that no bits in the SPMODE
register are allowed to change while the enable (EN) bit is set.

This driver changes the character length bits (LEN) while the enable
(EN) bit is set. Clearing the EN bit while changing the LEN bits makes
the driver work correctly on MPC8308RDB.

Signed-off-by: Ira W. Snyder 
Signed-off-by: Kim Phillips

spi: xilinx: Remove unused variable

2012-09-11T07:24:56+00:00

Warning is:

xilinx_spi.c: In function 'spi_setup_slave':
xilinx_spi.c:81: warning: unused variable 'regs'

Signed-off-by: Stephan Linz 
CC: Michal Simek

Tegra: Change Tegra20 to Tegra in common code, prep for T30

2012-09-10T20:01:24+00:00

Convert TEGRA20_ defines to either TEGRA_ or NV_PA_ where appropriate.
Convert tegra20_ source file and function names to tegra_, also.

Upcoming Tegra30 port will use common code/defines/names where possible.

Signed-off-by: Tom Warren 
Acked-by: Stephen Warren

MX28: SPI: Fix the DMA chaining

2012-09-06T12:17:55+00:00

It turns out that in order for the SPI DMA to properly support
continuous transfers longer than 65280 bytes, there are some very
important parts that were left out from the documentation.

Firstly, the XFER_SIZE register is not written with the whole length
of a transfer, but is written by each and every chained descriptor
with the length of the descriptors data buffer.

Next, unlike the demo code supplied by FSL, which only writes one PIO
word per descriptor, this does not apply if the descriptors are chained,
since the XFER_SIZE register must be written. Therefore, it is essential
to use four PIO words, CTRL0, CMD0, CMD1, XFER_SIZE. CMD0 and CMD1 are
written with zero, since they don't apply. The DMA programs the PIO words
in an incrementing order, so four PIO words.

Finally, unlike the demo code supplied by FSL, the SSP_CTRL0_IGNORE_CRC
must not be set during the whole transfer, but it must be set only on the
last descriptor in the chain.

Signed-off-by: Marek Vasut 
Cc: Fabio Estevam 
Cc: Otavio Salvador 
Cc: Stefano Babic

MX28: SPI: Fix the DMA DCache race condition

2012-09-06T12:17:55+00:00

This patch fixes dcache-related problem. The problem manifested
when dcache was enabled and the following command issued twice:

mw 0x42000000 0 0x4000 ; sf probe ; sf read 0x42000000 0x0 0x10000 ; sha1sum 0x42000000 0x10000

The SHA1 checksum was correct during the first call. Yet with
every subsequent call of the above command, it differed and was
wrong.

It turns out this was because of a race condition. On the first
time the command was called, no cacheline contained any data from
the destination memory location. The DMA transfered data into the
location and the cache above the location was invalidated. Then the
checksum was computed, but that meant the data were loaded into data
cache.

On any subsequent call, the DMA again transfered data into the same
destination. Yet during the transfer, some of the DCache lines were
evicted and written back into the main memory. Once the DMA transfer
completed, the data cache was invalidated over the memory location as
usual. But the data that were to be loaded back into the data cache
by subsequent SHA1 checksuming were corrupted.

Signed-off-by: Marek Vasut 
Cc: Fabio Estevam 
Cc: Otavio Salvador 
Cc: Stefano Babic

kw_spi: fix clock prescaler computation

2012-09-03T11:58:51+00:00

The computation was not correct with low clock values: setting a 1MHz
clock would result in an overlap that would then configure a 25Mhz
clock.

This patch implements a correct computation method according to the
kirkwood functionnal spec. table 600 (Serial Memory Interface
Configuration Register).

Signed-off-by: Valentin Longchamp 
cc: Holger Brunck 
cc: Prafulla Wadaskar 
Acked-by: Prafulla Wadaskar 

Signed-off-by: Prafulla Wadaskar

spi: atmel: add WDRBT bit to avoid receive overrun

2012-09-01T15:06:14+00:00

The atmel at91sam9x5 series spi has feature to avoid receive overren

Using the patch to enable it

Signed-off-by: Bo Shen 
Acked-by: Andreas Bießmann 
Signed-off-by: Andreas Bießmann