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<title>u-boot.git/drivers/spi, branch v2013.01-rc2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/spi?h=v2013.01-rc2</id>
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<updated>2012-10-26T05:00:28Z</updated>
<entry>
<title>Merge remote-tracking branch 'u-boot-ti/master'</title>
<updated>2012-10-26T05:00:28Z</updated>
<author>
<name>Albert ARIBAUD</name>
<email>albert.u.boot@aribaud.net</email>
</author>
<published>2012-10-26T05:00:28Z</published>
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<id>urn:sha1:c68436fa427a69ea308d74c410067507d6c7103b</id>
<content type='text'>
</content>
</entry>
<entry>
<title>omap3_spi: introduce CONFIG_OMAP3_SPI_D0_D1_SWAPPED</title>
<updated>2012-10-25T18:30:50Z</updated>
<author>
<name>Peter Korsgaard</name>
<email>peter.korsgaard@barco.com</email>
</author>
<published>2012-10-17T09:20:46Z</published>
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<id>urn:sha1:22cbeed454087ffa6ae6e56880bfff125497619b</id>
<content type='text'>
D0/D1 Swapped or not is a board property, not anything specific to
the am33xx SoC, so add a custom define for it.

At the same time correct the bit handling for the swapped mode
(DPE0 should be cleared and SI/DPE1 set).

Signed-off-by: Peter Korsgaard &lt;peter.korsgaard@barco.com&gt;
</content>
</entry>
<entry>
<title>powerpc/espi: remove write command length check</title>
<updated>2012-10-22T20:52:46Z</updated>
<author>
<name>Shaohui Xie</name>
<email>Shaohui.Xie@freescale.com</email>
</author>
<published>2012-10-11T20:31:46Z</published>
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<id>urn:sha1:9905757e298f37c59587d1a07b1ad8cdbed4e063</id>
<content type='text'>
Current espi controller driver assumes the command length of write command is
not equal to '1', it was made based on SPANSION SPI flash, but some SPI flash
driver such as SST does use write command length as '1', so write command on
SST SPI flash will not work. And the length check for write command is not
necessary for SPANSION, though it's harmless for SPANSION, it will stop write
operation on flashes like SST, so we remove the check.

Signed-off-by: Shaohui Xie &lt;Shaohui.Xie@freescale.com&gt;
Signed-off-by: Andy Fleming &lt;afleming@freescale.com&gt;
</content>
</entry>
<entry>
<title>Tegra20: Move some include files to arch-tegra for sharing with Tegra30</title>
<updated>2012-10-15T18:54:06Z</updated>
<author>
<name>Tom Warren</name>
<email>twarren@nvidia.com</email>
</author>
<published>2012-09-19T22:50:56Z</published>
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<id>urn:sha1:150c24936b70ce36e11069038ba8e955704cab3a</id>
<content type='text'>
The move is pretty straight-forward. ap20.h and tegra20.h were renamed to ap.h and tegra.h.
Some files remain in arch-tegra20 but 'include' a file in 'arch-tegra' with #defines &amp; structs
that will be common between T20 and T30 HW. HW-specific #defines, etc. stay in the 'arch-tegra20'
'root' file.

All boards build OK w/MAKEALL -s tegra20. Checkpatch.pl runs clean. Seaboard works OK.

Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>Merge branch 'master' of git://git.denx.de/u-boot-arm</title>
<updated>2012-09-21T21:53:13Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@ti.com</email>
</author>
<published>2012-09-21T21:53:13Z</published>
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<id>urn:sha1:495dbd72dd1172de866ba323263a5b62cf454972</id>
<content type='text'>
</content>
</entry>
<entry>
<title>Merge remote-tracking branch 'u-boot-imx/master'</title>
<updated>2012-09-20T22:26:19Z</updated>
<author>
<name>Albert ARIBAUD</name>
<email>albert.u.boot@aribaud.net</email>
</author>
<published>2012-09-20T22:26:19Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=d193c1b6eb05041c94ad9aacd8c94189d1dbc5f8'/>
<id>urn:sha1:d193c1b6eb05041c94ad9aacd8c94189d1dbc5f8</id>
<content type='text'>
</content>
</entry>
<entry>
<title>ColdFire: Queued SPI driver</title>
<updated>2012-09-20T12:39:27Z</updated>
<author>
<name>Richard Retanubun</name>
<email>RichardRetanubun@RuggedCom.com</email>
</author>
<published>2011-03-24T08:58:11Z</published>
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<id>urn:sha1:59d0612252a0ffcb878a1891249d32a306a24fa6</id>
<content type='text'>
This patch adds a driver for Freescale Colfire Queued SPI bus.
Coded to work with 8 bits per transfer to use with SPI flash.
CPOL, CPHA, and CS_ACTIVE_HIGH can be configured.

Tested with MCF5270 which have 4 chip selects.

Activate by #define CONFIG_CF_QSPI in board config.

Signed-off-by: Richard Retanubun &lt;richardretanubun@ruggedcom.com&gt;
</content>
</entry>
<entry>
<title>mpc8xxx_spi: fix SPI support on MPC8308RDB</title>
<updated>2012-09-18T21:16:44Z</updated>
<author>
<name>Ira W. Snyder</name>
<email>iws@ovro.caltech.edu</email>
</author>
<published>2012-09-12T21:17:31Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=f138ca1373d7ec9fca33ae21f1b5ff3898fd493f'/>
<id>urn:sha1:f138ca1373d7ec9fca33ae21f1b5ff3898fd493f</id>
<content type='text'>
The MPC8308RDB Reference Manual states that no bits in the SPMODE
register are allowed to change while the enable (EN) bit is set.

This driver changes the character length bits (LEN) while the enable
(EN) bit is set. Clearing the EN bit while changing the LEN bits makes
the driver work correctly on MPC8308RDB.

Signed-off-by: Ira W. Snyder &lt;iws@ovro.caltech.edu&gt;
Signed-off-by: Kim Phillips &lt;kim.phillips@freescale.com&gt;
</content>
</entry>
<entry>
<title>spi: xilinx: Remove unused variable</title>
<updated>2012-09-11T07:24:56Z</updated>
<author>
<name>Stephan Linz</name>
<email>linz@li-pro.net</email>
</author>
<published>2012-08-07T21:29:39Z</published>
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<id>urn:sha1:03afad2fc90dcff42402b0183f4b4f5119f99a18</id>
<content type='text'>
Warning is:

xilinx_spi.c: In function 'spi_setup_slave':
xilinx_spi.c:81: warning: unused variable 'regs'

Signed-off-by: Stephan Linz &lt;linz@li-pro.net&gt;
CC: Michal Simek &lt;monstr@monstr.eu&gt;
</content>
</entry>
<entry>
<title>Tegra: Change Tegra20 to Tegra in common code, prep for T30</title>
<updated>2012-09-10T20:01:24Z</updated>
<author>
<name>Tom Warren</name>
<email>twarren@nvidia.com</email>
</author>
<published>2012-09-05T00:00:24Z</published>
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<id>urn:sha1:29f3e3f24832fccdd7ce5fa961bc4d4005b07381</id>
<content type='text'>
Convert TEGRA20_ defines to either TEGRA_ or NV_PA_ where appropriate.
Convert tegra20_ source file and function names to tegra_, also.

Upcoming Tegra30 port will use common code/defines/names where possible.

Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
Acked-by: Stephen Warren &lt;swarren@nvidia.com&gt;
</content>
</entry>
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