u-boot.git/drivers/spi, branch v2013.07

Merge branch 'master' of git://git.denx.de/u-boot-arm

2013-07-12T14:36:48+00:00

Fix a trivial conflict in arch/arm/dts/exynos5250.dtsi about gpio and
serial.

Conflicts:
	arch/arm/dts/exynos5250.dtsi

Signed-off-by: Tom Rini

Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'

2013-06-28T15:51:13+00:00

spi: mxc_spi: Update pre and post divider algorithm

2013-06-26T14:23:30+00:00

The spi clock divisor is of the form x * (2**y),  or  x  << y, where x is
1 to 16, and y is 0 to 15. Note the similarity with floating point numbers.
Convert the desired divisor to the smallest number which is >= desired divisor,
and can be represented in this form. The previous algorithm chose a divisor
which could be almost twice as large as needed.

Signed-off-by: Troy Kisky 
Signed-off-by: Dirk Behme

spi: mxc_spi: Fix pre and post divider calculation

2013-06-26T14:22:51+00:00

Fix two issues with the calculation of pre_div and post_div:

1. pre_div: While the calculation of pre_div looks correct, to set the
CONREG[15-12] bits pre_div needs to be decremented by 1:

The i.MX 6Dual/6Quad Applications Processor Reference Manual (IMX6DQRM
Rev. 0, 11/2012) states:

CONREG[15-12]: PRE_DIVIDER
0000 Divide by 1
0001 Divide by 2
0010 Divide by 3
...
1101 Divide by 14
1110 Divide by 15
1111 Divide by 16

I.e. if we want to divide by 2, we have to write 1 to CONREG[15-12].

2. In case the post divider becomes necessary, pre_div will be divided by
16. So set pre_div to 16, too. And not 15.

Both issues above are tested using the following examples:

clk_src = 60000000 (60MHz, default i.MX6 ECSPI clock)

a) max_hz == 23000000 (23MHz, max i.MX6 ECSPI read clock)

-> pre_div =  3 (divide by 3 => CONREG[15-12] == 2)
-> post_div = 0 (divide by 1 => CONREG[11- 8] == 0)
               => 60MHz / 3 = 20MHz SPI clock

b) max_hz == 2000000 (2MHz)

-> pre_div =  16 (divide by 16 => CONREG[15-12] == 15)
-> post_div = 1  (divide by  2 => CONREG[11- 8] == 1)
               => 60MHz / 32 = 1.875MHz SPI clock

c) max_hz == 1000000 (1MHz)

-> pre_div =  16 (divide by 16 => CONREG[15-12] == 15)
-> post_div = 2  (divide by  4 => CONREG[11- 8] == 2)
               => 60MHz / 64 = 937.5kHz SPI clock

d) max_hz == 500000 (500kHz)

-> pre_div =  16 (divide by 16 => CONREG[15-12] == 15)
-> post_div = 3  (divide by  8 => CONREG[11- 8] == 3)
               => 60MHz / 128 = 468.75kHz SPI clock

Signed-off-by: Dirk Behme

cros: exynos: add SPI support for cros_ec

2013-06-26T14:13:24+00:00

This patch adds SPI support for carrying out the cros_ec protocol.

Signed-off-by: Hung-ying Tyan 
Signed-off-by: Randall Spangler 
Signed-off-by: Simon Glass 
Acked-by: Simon Glass

spi: mxc_spi: Use DIV_ROUND_UP at appropriate places

2013-06-22T17:38:01+00:00

This change slightly improves readability.

Signed-off-by: Axel Lin 
Reviewed-by: Jagannadha Sutradharudu Teki

spi: cf_qspi: Use DIV_ROUND_UP at appropriate place

2013-06-22T17:38:01+00:00

This change slightly improves readability.

Signed-off-by: Axel Lin 
Signed-off-by: Richard Retanubun 
Reviewed-by: Jagannadha Sutradharudu Teki

Merge branch 'master' of git://git.denx.de/u-boot-spi

2013-06-13T19:18:35+00:00

spi: tegra20_sflash: Remove redundant code to set bus and cs of struct spi_slave

2013-06-13T17:25:30+00:00

It's done in spi_alloc_slave(), thus remove the redundant code.

Signed-off-by: Axel Lin 
Acked-by: Marek Vasut 
Reviewed-by: Jagannadha Sutradharudu Teki

spi: tegra114_spi: Convert to use spi_alloc_slave()

2013-06-13T17:25:24+00:00

Signed-off-by: Axel Lin 
Acked-by: Marek Vasut 
Reviewed-by: Jagannadha Sutradharudu Teki