u-boot.git/drivers/spi, branch v2013.10

spi: mxc_spi: Fix double incrementing read pointer for unaligned buffers

2013-10-15T18:44:30+00:00

If dout buffer is not 32 bit-aligned or data to transmit is not multiple
of 32 bit the read data pointer is already incremented on single byte reads.

Signed-off-by: Timo Herbrecher 
Signed-off-by: Jagannadha Sutradharudu Teki

spi: Add GPL-2.0+ SPDX-License-Identifier for missing files

2013-10-15T18:44:01+00:00

Added GPL-2.0+ SPDX-License-Identifier for missed spi
source files.

Signed-off-by: Jagannadha Sutradharudu Teki

Coding Style cleanup: replace leading SPACEs by TABs

2013-10-14T20:06:54+00:00

Signed-off-by: Wolfgang Denk 
[trini: Drop changes for PEP 4 following python tools]
Signed-off-by: Tom Rini

Coding Style cleanup: remove trailing white space

2013-10-14T20:06:53+00:00

Signed-off-by: Wolfgang Denk

spi: exynos: Support word transfers

2013-10-08T12:48:12+00:00

Since SPI register access is so expensive, it is worth transferring data
a word at a time if we can. This complicates the driver unfortunately.

Use the byte-swapping feature to avoid having to convert to/from big
endian in software.

This change increases speed from about 2MB/s to about 4.5MB/s.

Signed-off-by: Simon Glass 
Signed-off-by: Rajeshwari S Shinde 
Reviewed-by: Jagannadha Sutradharudu Teki

spi: exynos: Minimise access to SPI FIFO level

2013-10-08T12:48:11+00:00

Accessing SPI registers is slow, but access to the FIFO level register
in particular seems to be extraordinarily expensive (I measure up to
600ns). Perhaps it is required to synchronise with the SPI byte output
logic which might run at 1/8th of the 40MHz SPI speed (just a guess).

Reduce access to this register by filling up and emptying FIFOs
more completely, rather than just one word each time around the inner
loop.

Since the rxfifo value will now likely be much greater that what we read
before we fill the txfifo, we only fill the txfifo halfway. This is
because if the txfifo is empty, but the rxfifo has data in it, then writing
too much data to the txfifo may overflow the rxfifo as data arrives.

This speeds up SPI flash reading from about 1MB/s to about 2MB/s on snow.

Signed-off-by: Simon Glass 
Signed-off-by: Rajeshwari S Shinde 
Reviewed-by: Jagannadha Sutradharudu Teki

spi: exynos: Support a delay after deactivate

2013-10-08T12:48:11+00:00

For devices that need some time to react after a spi transaction
finishes, add the ability to set a delay.

Implement this as a delay on the first/next transaction to avoid
any delay in the fairly common case where a SPI transaction is
followed by other processing.

Signed-off-by: Simon Glass 
Signed-off-by: Rajeshwari S Shinde 
Reviewed-by: Jagannadha Sutradharudu Teki

spi: add TI QSPI driver

2013-10-07T12:25:51+00:00

Adds a SPI master driver for the TI QSPI peripheral.
- Added quad read support.
- Added memory mapped support.

Signed-off-by: Matt Porter 
Signed-off-by: Sourav Poddar 
Signed-off-by: Jagannadha Sutradharudu Teki

spi: mxs_spi: Configure chipselect after block reset

2013-08-27T14:09:39+00:00

The chipselect must be written into the CTRL0 register after the SSP
block is reset, otherwise the block will always use ChipSelect #0.

Signed-off-by: Marek Vasut 
Cc: Fabio Estevam 
Cc: Jagannadha Sutradharudu Teki 
Cc: Otavio Salvador 
Cc: Stefano Babic 
Acked-by: Stefano Babic

powerpc: Fix CamelCase checkpatch warnings

2013-08-20T16:57:51+00:00

85xx, 86xx PowerPC folders have code variables with CamelCase naming conventions.
because of this code checkpatch script generates "WARNING: Avoid CamelCase".

Convert variables name to normal naming convention and modify board, driver
files with updated the new structure.

Signed-off-by: Prabhakar Kushwaha 
Acked-by: York Sun