u-boot.git/drivers/spi, branch v2013.10-rc2

powerpc: Fix CamelCase checkpatch warnings

2013-08-20T16:57:51Z

85xx, 86xx PowerPC folders have code variables with CamelCase naming conventions. because of this code checkpatch script generates "WARNING: Avoid CamelCase". Convert variables name to normal naming convention and modify board, driver files with updated the new structure. Signed-off-by: Prabhakar Kushwaha Acked-by: York Sun

spi: Add zynq spi controller driver

2013-08-06T19:39:47Z

Zynq spi controller driver supports 2 buses and 3 chipselects on each bus. Signed-off-by: Jagannadha Sutradharudu Teki Acked-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek

spi: mpc8xxx_spi: Use DIV_ROUND_UP instead of open-coded

2013-08-06T18:28:24Z

Use DIV_ROUND_UP to simplify the code. Signed-off-by: Axel Lin

spi: fsl_espi: Use DIV_ROUND_UP instead of open-coded

2013-08-06T18:28:09Z

Use DIV_ROUND_UP to simplify the code. Signed-off-by: Axel Lin

spi: bfin_spi: Use DIV_ROUND_UP instead of open-coded

2013-07-31T08:56:04Z

Use DIV_ROUND_UP to simplify the code. Signed-off-by: Axel Lin Signed-off-by: Scott Jiang Signed-off-by: Sonic Zhang

Add GPL-2.0+ SPDX-License-Identifier to source files

2013-07-24T13:44:38Z

Signed-off-by: Wolfgang Denk [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini

Merge branch 'master' of git://git.denx.de/u-boot-arm

2013-07-12T14:36:48Z

Fix a trivial conflict in arch/arm/dts/exynos5250.dtsi about gpio and serial. Conflicts: arch/arm/dts/exynos5250.dtsi Signed-off-by: Tom Rini

Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'

2013-06-28T15:51:13Z

spi: mxc_spi: Update pre and post divider algorithm

2013-06-26T14:23:30Z

The spi clock divisor is of the form x * (2**y), or x << y, where x is 1 to 16, and y is 0 to 15. Note the similarity with floating point numbers. Convert the desired divisor to the smallest number which is >= desired divisor, and can be represented in this form. The previous algorithm chose a divisor which could be almost twice as large as needed. Signed-off-by: Troy Kisky Signed-off-by: Dirk Behme

spi: mxc_spi: Fix pre and post divider calculation

2013-06-26T14:22:51Z

Fix two issues with the calculation of pre_div and post_div: 1. pre_div: While the calculation of pre_div looks correct, to set the CONREG[15-12] bits pre_div needs to be decremented by 1: The i.MX 6Dual/6Quad Applications Processor Reference Manual (IMX6DQRM Rev. 0, 11/2012) states: CONREG[15-12]: PRE_DIVIDER 0000 Divide by 1 0001 Divide by 2 0010 Divide by 3 ... 1101 Divide by 14 1110 Divide by 15 1111 Divide by 16 I.e. if we want to divide by 2, we have to write 1 to CONREG[15-12]. 2. In case the post divider becomes necessary, pre_div will be divided by 16. So set pre_div to 16, too. And not 15. Both issues above are tested using the following examples: clk_src = 60000000 (60MHz, default i.MX6 ECSPI clock) a) max_hz == 23000000 (23MHz, max i.MX6 ECSPI read clock) -> pre_div = 3 (divide by 3 => CONREG[15-12] == 2) -> post_div = 0 (divide by 1 => CONREG[11- 8] == 0) => 60MHz / 3 = 20MHz SPI clock b) max_hz == 2000000 (2MHz) -> pre_div = 16 (divide by 16 => CONREG[15-12] == 15) -> post_div = 1 (divide by 2 => CONREG[11- 8] == 1) => 60MHz / 32 = 1.875MHz SPI clock c) max_hz == 1000000 (1MHz) -> pre_div = 16 (divide by 16 => CONREG[15-12] == 15) -> post_div = 2 (divide by 4 => CONREG[11- 8] == 2) => 60MHz / 64 = 937.5kHz SPI clock d) max_hz == 500000 (500kHz) -> pre_div = 16 (divide by 16 => CONREG[15-12] == 15) -> post_div = 3 (divide by 8 => CONREG[11- 8] == 3) => 60MHz / 128 = 468.75kHz SPI clock Signed-off-by: Dirk Behme