u-boot.git/drivers/spi, branch v2014.01

Merge branch 'master' of git://git.denx.de/u-boot-arm

2014-01-16T18:50:16+00:00

spi: sh_qspi: Add header file that defines the address of registers

2014-01-15T23:07:20+00:00

Signed-off-by: Nobuhiro Iwamatsu 
Reviewed-by: Jagannadha Sutradharudu Teki 
Signed-off-by: Nobuhiro Iwamatsu

spi: sh_spi: Use sh_spi_clear_bit() instead of open-coded

2014-01-11T06:51:31+00:00

We have a sh_spi_clear_bit() function, there's no reason not to use it.

Signed-off-by: Axel Lin 
Acked-by: Nobuhiro Iwamatsu 
Reviewed-by: Jagannadha Sutradharudu Teki

spi: Add Faraday SPI controller support

2014-01-11T06:51:30+00:00

The Faraday FTSSP010 is a multi-function controller
which supports I2S/SPI/SSP/AC97/SPDIF. However This
patch implements only the SPI mode.

NOTE:
The DMA and CS/Clock control logic has been altered
since hardware revision 1.19.0. So this patch
would first detects the revision id of the underlying
chip, and then switch to the corresponding software
control routines.

Signed-off-by: Kuo-Jung Su 
Signed-off-by: Jagannadha Sutradharudu Teki 
CC: Tom Rini

spi: tegra: clear RDY bit prior to every transfer

2013-12-18T18:30:51+00:00

The RDY bit indicates that a transfer is complete. This needs to be
cleared by SW before every single HW transaction, rather than only
at the start of each SW transaction (those being made up of n HW
transactions).

It seems that earlier HW may have cleared this bit autonomously when
starting a new transfer, and hence this code was not needed in practice.
However, this is generally a good idea in all cases. In Tegra124, the
HW behaviour appears to have changed, and SW must explicitly clear this
bit. Otherwise, SW will believe that transfers have completed when they
have not, and may e.g. read stale data from the RX FIFO.

Signed-off-by: Yen Lin 
[swarren, rewrote commit description, unified duplicate RDY clearing code
and moved it right before the start of the HW transaction, unconditionally
exit loop after reading RX data, rather than checking if TX FIFO is empty,
since it is guaranteed to be]
Signed-off-by: Stephen Warren 
Reviewed-by: Jagannadha Sutradharudu Teki

spi: Add support SH Quad SPI driver

2013-12-18T17:53:41+00:00

This patch adds a driver for Renesas SoC's Quad SPI bus.
This supports with 8 bits per transfer to use with SPI flash.

Signed-off-by: Kouei Abe 
Signed-off-by: Nobuhiro Iwamatsu 
Signed-off-by: Jagannadha Sutradharudu Teki

Merge branch 'spi' of git://git.denx.de/u-boot-x86

2013-12-10T14:36:23+00:00

sandbox: spi: Add SPI emulation bus

2013-12-09T19:22:18+00:00

This adds a SPI framework for people to hook up simulated SPI clients.

Signed-off-by: Mike Frysinger 
Signed-off-by: Simon Glass

spi_flash: Add spi_flash_probe_fdt() to locate SPI by FDT node

2013-12-09T19:22:12+00:00

This allows us to put the SPI flash chip inside the SPI interface node,
with U-Boot finding the correct bus and chip select automatically.

Signed-off-by: Simon Glass

spi: bfin_spi6xx: Remove unnecessary test for bus and pins[bus]

2013-12-06T08:06:51+00:00

For invalid bus number, current code returns NULL in the default case of
switch-case statements. In additional, pins[bus] is always not NULL because
it is the address of specific row of the two-dimensional array.
Thus this patch removes these unnecessary test.

Signed-off-by: Axel Lin 
Acked-by: Scott Jiang 
Signed-off-by: Sonic Zhang