u-boot.git/drivers/spi, branch v2014.04-rc2

Merge branch 'master' of git://git.denx.de/u-boot-spi

2014-02-21T13:00:22Z

blackfin: add spi and i2c specific get clock functions

2014-02-20T05:46:56Z

Signed-off-by: Sonic Zhang

spi: ti_qspi: Add delay before xfer for am43xx

2014-02-18T17:11:09Z

Without this delay, write/read is failing. Looks like, the WIP always remain set and hence a timeout occurs leading to the error. Without this patch, device does not get probed also. Here is the log. U-Boot# U-Boot# U-Boot# U-Boot# sf probe 0 SF: Unsupported flash IDs: manuf ff, jedec ffff, ext_jedec ffff Failed to initialize SPI flash at 0:0 U-Boot# sf probe 0 While with this patch, log is U-Boot# sf probe 0 SF: Detected MX25L51235F with page size 256 Bytes, erase size 64 KiB, total 64 MiB, mapped at 30000000 U-Boot# sf erase 0 0x80000 SF: 524288 bytes @ 0x0 Erased: OK U-Boot# mw 81000000 0xdededede 0x40000 U-Boot# sf write 81000000 0 0x40000 SF: 262144 bytes @ 0x0 Written: OK U-Boot# sf read 82000000 0 0x40000 SF: 262144 bytes @ 0x0 Read: OK U-Boot# md 0x82000000 Signed-off-by: Sourav Poddar Reviewed-by: Jagannadha Sutradharudu Teki

spi: ti_qspi: Add AM43xx specifics changes

2014-02-18T17:11:09Z

Add AM43xx specific changes. Signed-off-by: Sourav Poddar Reviewed-by: Jagannadha Sutradharudu Teki

spi: spi-mxc: implement clk control for ECSPI to fix SPI_MODE_3

2014-02-18T16:59:26Z

SPI_MODE_3 requires clk high when inactive. The SCLK_CTL field of the config reg was not configured in case of CPOL. Fix configuration so that SPI_MODE_3 which uses CPOL configures the clk line to be high in inactive state. Signed-off-by: Markus Niebel Reviewed-by: Jagannadha Sutradharudu Teki

spi: xilinx: Move timeout calculation out of the loop

2014-02-18T16:54:28Z

Timeout calculation should be out of the data loop. This patch increase spi bandwidth for 30%. Signed-off-by: Michal Simek Reviewed-by: Jagannadha Sutradharudu Teki

Merge branch 'master' of git://git.denx.de/u-boot-arm

2014-01-16T18:50:16Z

spi: sh_qspi: Add header file that defines the address of registers

2014-01-15T23:07:20Z

Signed-off-by: Nobuhiro Iwamatsu Reviewed-by: Jagannadha Sutradharudu Teki Signed-off-by: Nobuhiro Iwamatsu

spi: sh_spi: Use sh_spi_clear_bit() instead of open-coded

2014-01-11T06:51:31Z

We have a sh_spi_clear_bit() function, there's no reason not to use it. Signed-off-by: Axel Lin Acked-by: Nobuhiro Iwamatsu Reviewed-by: Jagannadha Sutradharudu Teki

spi: Add Faraday SPI controller support

2014-01-11T06:51:30Z

The Faraday FTSSP010 is a multi-function controller which supports I2S/SPI/SSP/AC97/SPDIF. However This patch implements only the SPI mode. NOTE: The DMA and CS/Clock control logic has been altered since hardware revision 1.19.0. So this patch would first detects the revision id of the underlying chip, and then switch to the corresponding software control routines. Signed-off-by: Kuo-Jung Su Signed-off-by: Jagannadha Sutradharudu Teki CC: Tom Rini