u-boot.git/drivers/spi, branch v2015.01

qspi:fsl implement AHB read

2015-01-08T18:33:28+00:00

The QSPI controller in i.MX 6SoloX and Vybrid supports reading data using
IP register and AHB bus.

The original driver only supports reading data from IP interface. The IC
team suggests to use AHB read which is faster then IP read. Using AHB read,
we can directly memcpy, a "missed" access to the buffer will cause the
controller to clear the buffer and use the SEQID stored in bfgencr register
to initiate a read from flash device.

Since AHB bus is 64 bit width, we can not set MCR register using 32bit. In
order to minimize code change, redefine QSPI_MCR_END_CFD_LE to 64bit Little
endian but not 32bit Little endia.

Introduce a new configuration option CONFIG_SYS_FSL_QSPI_AHB. If want to
use AHB read, just define CONFIG_SYS_FSL_QSPI_AHB. If not, just ignore it.
Actually if Vybrid is migrated to use AHB read, this option can be removed and
IP read function can be discared. The reason to introduce this option
is that only i.MX SOC is tested in my side, no Vybrid platform for me.

In spi_setup_slave, the original piece code to set AHB is deleted, since
Vybrid platform does not use this to intiate AHB read. Instead, add
qspi_init_ahb_read function if defined CONFIG_SYS_FSL_QSPI_AHB.

Signed-off-by: Peng Fan 
Reviewed-by: Jagannadha Sutradharudu Teki

spi: ftssp010_spi: Simplify code flow in ftssp010_[wait|wait_tx|wait_rx]

2015-01-08T06:32:55+00:00

No functional change, just simplify the code a bit.

Signed-off-by: Axel Lin 
Reviewed-by: Jagannadha Sutradharudu Teki

spi: cadence_qspi: Fix checking return value of fdt_first_subnode()

2015-01-07T07:00:54+00:00

fdt_first_subnode() returns -FDT_ERR_NOTFOUND if no subnode found.
0 is supposed to be a valid offset returns from fdt_first_subnode().

Signed-off-by: Axel Lin 
Reviewed-by: Jagannadha Sutradharudu Teki

spi:fsl-quadspi support bank register read write

2015-01-07T06:55:05+00:00

To support bigger than 16MB size qspi flashes, spi framework uses bank
switch to access higher bank or lower bank.

In this patch, QSPI_CMD_BRRD, QSPI_CMD_BRWR, QSPI_CMD_WREAR, QSPI_CMD_RDEAR
is initialized in LUT register with related pad and length configuration.
qspi_op_pp is originally for page programming, this patch reuses this function
for bank register switch and renamed it with qspi_op_write.

Since bank or EAR register is only 1 byte length, however original qspi_op_pp
or now renamed qspi_op_write only support 4 bytes lenght as the access unit,
this will trigger data abort exception when access EAR or bank register.
This is because upper framework passes a 1 bytes pointer to qspi_op_write,
however qspi_op_write treat it as an int pointer. This patch fixes this for
accessing EAR or bank register.

Signed-off-by: Peng Fan 
Reviewed-by: Jagannadha Sutradharudu Teki

dt: socfpga: Rename snps, dw-spi-mmio to snps, dw-apb-ssi

2015-01-06T10:32:58+00:00

Linux now also contains SPI driver, yet the name is 'snps,dw-apb-ssi'.
Fix the naming before we have to support both names.

Signed-off-by: Marek Vasut 
Cc: Chin Liang See 
Cc: Dinh Nguyen 
Cc: Pavel Machek 
Cc: Stefan Roese 
Cc: Vince Bridgers 
Reviewed-by: Stefan Roese 
Acked-by: Pavel Machek 
Reviewed-by: Jagannadha Sutradharudu Teki

spi: designware_spi: Fix detecting FIFO depth

2015-01-06T10:22:27+00:00

Current code tries to find the highest valid fifo depth by checking the value
it wrote to DW_SPI_TXFLTR. There are a few problems in current code:
1) There is an off-by-one in dws->fifo_len setting because it assumes the latest
   register write fails so the latest valid value should be fifo - 1.
2) We know the depth could be from 2 to 256 from HW spec, so it is not necessary
   to test fifo == 257. In the case fifo is 257, it means the latest valid
   setting is fifo = 256. So after the for loop iteration, we should check
   fifo == 2 case instead of fifo == 257 if detecting the FIFO depth fails.
This patch fixes above issues.

Signed-off-by: Axel Lin 
Acked-by: Stefan Roese 
Reviewed-by: Jagannadha Sutradharudu Teki

imx:qspi add 4K erase support

2014-12-31T09:22:32+00:00

Add 4k erase command support for qspi driver. reuse the 64k erase function,
but change the function name from qspi_op_se to qspi_op_erase, since it
supports 64k and 4k erase.

Signed-off-by: Peng Fan 
Reviewed-by: Jagannadha Sutradharudu Teki

arm:mx6sx add QSPI support

2014-12-31T09:22:32+00:00

Add QSPI support for mx6solox.

Signed-off-by: Peng Fan 
Reviewed-by: Jagannadha Sutradharudu Teki

QuadSPI: use correct amba_base

2014-12-31T09:22:32+00:00

According cs, use different amba_base to choose the corresponding
flash devices.  If not, `sf probe 1:0` and `sf probe 1:1` will
choose the same flash device, but not different flash devices.

Signed-off-by: Peng Fan 
Reviewed-by: Jagannadha Sutradharudu Teki

QuadSPI: use QSPI_CMD_xx instead of flash opcodes

2014-12-31T09:22:32+00:00

Use QSPI_CMD_xx instead of flash opcodes

Signed-off-by: Peng Fan 
Reviewed-by: Jagannadha Sutradharudu Teki