u-boot.git/drivers/spi, branch v2015.01-rc4

Merge branch 'master' of git://git.denx.de/u-boot-socfpga

2014-12-16T14:41:00Z

x86: ich-spi: Add Intel Tunnel Creek SPI controller support

2014-12-14T05:32:05Z

Add Intel Tunnel Creek SPI controller support which is an ICH7 compatible device. Signed-off-by: Bin Meng Acked-by: Simon Glass

x86: ich-spi: Set the tx operation mode for ich 7

2014-12-13T22:08:04Z

ICH 7 SPI controller only supports byte program (02h) for SST flash. Word program (ADh) is not supported. Signed-off-by: Bin Meng Reviewed-by: Jagannadha Sutradharudu Teki

x86: ich-spi: Set the rx operation mode for ich 7

2014-12-13T22:08:04Z

ICH 7 SPI controller only supports array read command (03h). Fast array read command (0Bh) is not supported. Signed-off-by: Bin Meng Acked-by: Simon Glass Tested-by: Simon Glass Reviewed-by: Jagannadha Sutradharudu Teki

x86: ich-spi: Fix a bug of reading from a non-64 bytes aligned address

2014-12-13T22:08:04Z

The ich spi controller driver spi_xfer() tries to align reading address to 64 bytes when doing spi data in, which causes a bug of either infinite loop or a huge size memcpy(). Actually the ich spi controller does not have such requirement of 64 bytes alignment when reading data from spi slave devices. Signed-off-by: Bin Meng Acked-by: Simon Glass Tested-by: Simon Glass

spi: designware_spi: Some fixes / changes

2014-12-06T12:52:47Z

As suggested by Pavel, here some fixes to the designware SPI driver: - Spelling fixes - Comment for timeout added - Removed n_bytes completely (bits_per_word is enough for this) - Unput clock now not defined via macro. The function to get the clock value is now called directly from within the driver Signed-off-by: Stefan Roese Cc: Chin Liang See Cc: Dinh Nguyen Cc: Vince Bridgers Cc: Marek Vasut Acked-by: Pavel Machek Cc: Jagannadha Sutradharudu Teki

spi: Add designware master SPI DM driver used on SoCFPGA

2014-12-06T12:52:47Z

This patch adds the driver for the Designware master SPI controller. This IP core is integrated on the Altera SoCFPGA. This implementation is a driver model (DM) implementation. So multiple SPI drivers can be used. Thats necessary, since SoCFPGA also integrates the Cadence QSPI controller used to connect the SPI NOR flashes. Without DM, using multiple SPI drivers is not possible. This driver is very loosely based on the Linux driver. Most of the Linux driver is removed. Only the polling loop for the transfer is really used from this driver, as we don't support interrupts and DMA right now. This is tested on the SoCrates SoCFPGA board using the SPI pins on the P14 header. Signed-off-by: Stefan Roese Cc: Chin Liang See Cc: Dinh Nguyen Cc: Vince Bridgers Cc: Marek Vasut Cc: Pavel Machek Reviewed-by: Simon Glass Cc: Jagannadha Sutradharudu Teki

spi: Add Cadence QSPI DM driver used by SoCFPGA

2014-12-06T12:52:46Z

This driver is cloned from the Altera Rockerboard.org U-Boot repository. I used this git tag: ACDS14.0.1_REL_GSRD_RC2. With Some modification to support the U-Boot driver model (DM). As mentioned above, in this new version I ported this driver to the new driver model (DM). One big advantage of this move is that now multiple SPI drivers can be enabled on one platform. And since the SoCFPGA also has the Designware SPI master controller integrated, this feature is really needed to support both controllers. Because of this, this series needs the DT support for SoCFPGA to be applied. For DT based probing in the SPI DM. Signed-off-by: Stefan Roese Cc: Chin Liang See Cc: Dinh Nguyen Cc: Vince Bridgers Cc: Marek Vasut Cc: Pavel Machek Cc: Simon Glass Cc: Jagannadha Sutradharudu Teki

arm: omap: add support for am57xx devices

2014-12-04T16:04:14Z

just add a few ifdefs around because this device is very similar to dra7xxx. Signed-off-by: Felipe Balbi Reviewed-by: Tom Rini

Merge git://git.denx.de/u-boot-dm

2014-11-24T17:01:48Z

Conflicts: drivers/serial/serial-uclass.c Signed-off-by: Tom Rini