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<title>u-boot.git/drivers/spi, branch v2015.10</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>spi: tegra20: Add support for mode selection</title>
<updated>2015-10-11T11:13:06+00:00</updated>
<author>
<name>Mirza Krak</name>
<email>mirza.krak@hostmobility.com</email>
</author>
<published>2015-09-08T08:30:49+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=5cb1b7b395c0150e179f3b748d755cdc2f613a06'/>
<id>5cb1b7b395c0150e179f3b748d755cdc2f613a06</id>
<content type='text'>
Respect the mode passed in set_mode ops.

Signed-off-by: Mirza Krak &lt;mirza.krak@hostmobility.com&gt;
Reviewed-by: Jagan Teki &lt;jteki@openedev.com&gt;
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<pre>
Respect the mode passed in set_mode ops.

Signed-off-by: Mirza Krak &lt;mirza.krak@hostmobility.com&gt;
Reviewed-by: Jagan Teki &lt;jteki@openedev.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>spi: zynq_spi: Fix to configure CPOL, CPHA mask</title>
<updated>2015-10-11T11:13:06+00:00</updated>
<author>
<name>Jagan Teki</name>
<email>jteki@openedev.com</email>
</author>
<published>2015-09-07T20:08:50+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=a22bba81e40959c3675b794422508911034049d4'/>
<id>a22bba81e40959c3675b794422508911034049d4</id>
<content type='text'>
priv-&gt;mode is initialized when .set_speed triggers
with mode value, so checking mode for configuring
CPOL, CPHA using priv-&gt;mode is invalid hence use
mode from .set_speed argument, and at the end
priv-&gt;mode will initialized with mode.

This patch also replaces formatting string to use
speed instead of mode in .set_speed ops.

Signed-off-by: Jagan Teki &lt;jteki@openedev.com&gt;
</content>
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<pre>
priv-&gt;mode is initialized when .set_speed triggers
with mode value, so checking mode for configuring
CPOL, CPHA using priv-&gt;mode is invalid hence use
mode from .set_speed argument, and at the end
priv-&gt;mode will initialized with mode.

This patch also replaces formatting string to use
speed instead of mode in .set_speed ops.

Signed-off-by: Jagan Teki &lt;jteki@openedev.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>spi: xilinx_spi: Fix to configure CPOL, CPHA mask</title>
<updated>2015-10-11T11:13:06+00:00</updated>
<author>
<name>Jagan Teki</name>
<email>jteki@openedev.com</email>
</author>
<published>2015-09-07T19:56:29+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=d5f60737dbaac82f3f7d49eb03ece443beb70fc8'/>
<id>d5f60737dbaac82f3f7d49eb03ece443beb70fc8</id>
<content type='text'>
priv-&gt;mode is initialized when .set_speed triggers
with mode value, so checking mode for configuring
CPOL, CPHA using priv-&gt;mode is invalid hence use
mode from .set_speed argument, and at the end
priv-&gt;mode will initialized with mode.

This patch also replaces formatting string to use
speed instead of mode in .set_speed ops.

Signed-off-by: Jagan Teki &lt;jteki@openedev.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
priv-&gt;mode is initialized when .set_speed triggers
with mode value, so checking mode for configuring
CPOL, CPHA using priv-&gt;mode is invalid hence use
mode from .set_speed argument, and at the end
priv-&gt;mode will initialized with mode.

This patch also replaces formatting string to use
speed instead of mode in .set_speed ops.

Signed-off-by: Jagan Teki &lt;jteki@openedev.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>bitops: introduce BIT() definition</title>
<updated>2015-09-11T21:15:32+00:00</updated>
<author>
<name>Heiko Schocher</name>
<email>hs@denx.de</email>
</author>
<published>2015-09-07T11:43:52+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=92a3188d7d836779915e3a6f9251fa07b9c753e4'/>
<id>92a3188d7d836779915e3a6f9251fa07b9c753e4</id>
<content type='text'>
introduce BIT() definition, used in at91_udc gadget
driver.

Signed-off-by: Heiko Schocher &lt;hs@denx.de&gt;
[remove all other occurrences of BIT(x) definition]
Signed-off-by: Andreas Bießmann &lt;andreas.devel@googlemail.com&gt;
Acked-by: Stefan Roese &lt;sr@denx.de&gt;
Acked-by: Anatolij Gustschin &lt;agust@denx.de&gt;
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<pre>
introduce BIT() definition, used in at91_udc gadget
driver.

Signed-off-by: Heiko Schocher &lt;hs@denx.de&gt;
[remove all other occurrences of BIT(x) definition]
Signed-off-by: Andreas Bießmann &lt;andreas.devel@googlemail.com&gt;
Acked-by: Stefan Roese &lt;sr@denx.de&gt;
Acked-by: Anatolij Gustschin &lt;agust@denx.de&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Move ALLOC_CACHE_ALIGN_BUFFER() to the new memalign.h header</title>
<updated>2015-09-11T21:15:20+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2015-09-02T23:24:58+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=cf92e05c0135bc2b1a1b25a3218e31e6d79bad59'/>
<id>cf92e05c0135bc2b1a1b25a3218e31e6d79bad59</id>
<content type='text'>
Now that we have a new header file for cache-aligned allocation, we should
move the stack-based allocation macro there also.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
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<pre>
Now that we have a new header file for cache-aligned allocation, we should
move the stack-based allocation macro there also.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>rockchip: Add SPI driver</title>
<updated>2015-09-03T03:28:24+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2015-09-02T01:19:37+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=1b2fd5bf4eedfaf5af9d8fc219781fb521d12c7a'/>
<id>1b2fd5bf4eedfaf5af9d8fc219781fb521d12c7a</id>
<content type='text'>
Add a SPI driver for the Rockchip RK3288, using driver model. It should work
for other Rockchip SoCs also.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
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<pre>
Add a SPI driver for the Rockchip RK3288, using driver model. It should work
for other Rockchip SoCs also.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>dm: Use dev_get_addr() where possible</title>
<updated>2015-08-31T13:57:26+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2015-08-11T14:33:29+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=4e9838c102e8575fbff3944e1596a53ec579844a'/>
<id>4e9838c102e8575fbff3944e1596a53ec579844a</id>
<content type='text'>
This is a convenient way for a driver to get the hardware address of a
device, when regmap or syscon are not being used. Change existing callers
to use it as an example to others.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Joe Hershberger &lt;joe.hershberger@ni.com&gt;
Acked-by: Stephen Warren &lt;swarren@wwwdotorg.org&gt;
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<pre>
This is a convenient way for a driver to get the hardware address of a
device, when regmap or syscon are not being used. Change existing callers
to use it as an example to others.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Joe Hershberger &lt;joe.hershberger@ni.com&gt;
Acked-by: Stephen Warren &lt;swarren@wwwdotorg.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge branch 'master' of git://git.denx.de/u-boot-spi</title>
<updated>2015-08-18T12:25:24+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2015-08-18T12:25:24+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=952bd79b53f002740634977edfc0c4d744908032'/>
<id>952bd79b53f002740634977edfc0c4d744908032</id>
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<pre>
</pre>
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</entry>
<entry>
<title>spi: ti_qspi: Use DMA to read from qspi flash</title>
<updated>2015-08-17T17:59:15+00:00</updated>
<author>
<name>Vignesh R</name>
<email>vigneshr@ti.com</email>
</author>
<published>2015-08-17T09:50:13+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=8ddd9c485f17de4bea55707f5b9cf07fd0a89ed0'/>
<id>8ddd9c485f17de4bea55707f5b9cf07fd0a89ed0</id>
<content type='text'>
ti_qspi uses memory map mode for faster read. Enabling DMA will increase
read speed by 3x @48MHz on DRA74 EVM.

Signed-off-by: Vignesh R &lt;vigneshr@ti.com&gt;
Reviewed-by: Jagan Teki &lt;jteki@openedev.com&gt;
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<pre>
ti_qspi uses memory map mode for faster read. Enabling DMA will increase
read speed by 3x @48MHz on DRA74 EVM.

Signed-off-by: Vignesh R &lt;vigneshr@ti.com&gt;
Reviewed-by: Jagan Teki &lt;jteki@openedev.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ti: qspi: set flash quad bit based on quad support flag</title>
<updated>2015-08-17T17:59:14+00:00</updated>
<author>
<name>vishalm@ti.com</name>
<email>vishalm@ti.com</email>
</author>
<published>2015-08-17T15:47:51+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=a39cfe717c4152ececea5c4ce0aa2e97faa263ab'/>
<id>a39cfe717c4152ececea5c4ce0aa2e97faa263ab</id>
<content type='text'>
Update op_mode_rx flag based on CONFIG_QSPI_QUAD_SUPPORT flag,
instead of platform.

Signed-off-by: Vishal Mahaveer &lt;vishalm@ti.com&gt;
Reviewed-by: Jagan Teki &lt;jteki@openedev.com&gt;
</content>
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<pre>
Update op_mode_rx flag based on CONFIG_QSPI_QUAD_SUPPORT flag,
instead of platform.

Signed-off-by: Vishal Mahaveer &lt;vishalm@ti.com&gt;
Reviewed-by: Jagan Teki &lt;jteki@openedev.com&gt;
</pre>
</div>
</content>
</entry>
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