u-boot.git/drivers/spi, branch v2016.03-rc1

Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq

2016-01-27T20:05:36Z

spi: fsl_qspi: Fix qspi_op_rdsr memcpy issue

2016-01-27T16:28:31Z

In current driver, we always copy 4 bytes to the dest memory. Actually the dest memory may be shorter than 4 bytes. Add an argument to indicate the dest memory length. Avoid writing memory outside of the bounds. Signed-off-by: Gong Qianyu Reviewed-by: York Sun

spi: fsl_qspi: Fix qspi_op_rdid memcpy issue

2016-01-27T16:28:04Z

In current driver everytime we memcpy 4 bytes to the dest memory regardless of the remaining length. This patch adds checking the remaining length before memcpy. If the length is shorter than 4 bytes, memcpy the actual length of data to the dest memory. Signed-off-by: Gong Qianyu Reviewed-by: York Sun

spi: fsl_qspi: fix compile warning for 64-bit platform

2016-01-27T16:27:49Z

This patch fixes the following compile warning: drivers/spi/fsl_qspi.c: In function 'fsl_qspi_probe': drivers/spi/fsl_qspi.c:937:15: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] priv->regs = (struct fsl_qspi_regs *)plat->reg_base; ^ Just make the cast explicit. Signed-off-by: Gong Qianyu Reviewed-by: York Sun

dm: x86: spi: Convert ICH SPI driver to driver model PCI API

2016-01-24T04:07:17Z

At present this SPI driver works by searching the PCI buses for its peripheral. It also uses the legacy PCI API. In addition the driver has code to determine the type of Intel PCH that is used (version 7 or version 9). Now that we have proper PCH drivers we can use those to obtain the information we need. While the device tree has a node for the SPI peripheral it is not in the right place. It should be on the PCI bus as a sub-peripheral of the LPC device. Update the device tree files to show the SPI controller within the PCH, so that PCI access works as expected. This patch includes Bin's fix-up patch from here: https://patchwork.ozlabs.org/patch/569478/ Signed-off-by: Simon Glass Signed-off-by: Bin Meng Reviewed-by: Bin Meng Tested-by: Bin Meng

spi: ich: Separate out the read/write trace from normal debugging

2016-01-24T04:07:17Z

The trace is seldom useful for basic debugging. Allow it to be enabled separately so that it is easier to see the more important init and error debug messages. Signed-off-by: Simon Glass Reviewed-by: Bin Meng

rockchip: spi: Remove the explicit pinctrl setting

2016-01-22T03:42:36Z

The correct pinctrl is handled automatically so we don't need to do it in the driver. The exception is when we want to use a different chip select (other than 0). But this isn't used at present. Signed-off-by: Simon Glass

rockchip: spi: Correct chip-enable code

2016-01-22T03:42:36Z

At present there is an incorrect call to rkspi_enable_chip(). It should be disabling the chip, not enabling it. Correct this and ensure that the chip is disabled when releasing the bus. Signed-off-by: Simon Glass

rockchip: spi: Implement the delays

2016-01-22T03:42:36Z

Some devices need delays before and after activiation. Implement these features in the SPI driver so that we will be able to enable the Chrome OS EC. Signed-off-by: Simon Glass

rockchip: spi: Correct the bus init code

2016-01-22T03:42:35Z

Two of the init values are created locally so cannot be out of range. The masking is unnecessary and in one case is incorrect. Fix it. Signed-off-by: Simon Glass