u-boot.git/drivers/spi, branch v2016.09-rc1

dm: spi: Read default speed and mode values from DT

2016-07-09T14:46:34Z

In case of DT boot, don't read default speed and mode for SPI from CONFIG_*, instead read from DT node. This will make sure that boards with multiple SPI/QSPI controllers can be probed at different bus frequencies and SPI modes. Signed-off-by: Vignesh R Reviewed-by: Simon Glass Reviewed-by: Mugunthan V N Reviewed-by: Jagan Teki

spi: cadence_quadspi: Enable QUAD mode based on DT data

2016-07-09T14:46:33Z

Instead of relying on CONFIG_SPI_FLASH_QUAD to be defined to enable QUAD mode, make use of mode_rx field of dm_spi_slave_platdata to determine whether to enable or disable QUAD mode. This is necessary to support muliple SPI controllers where one of them may not support QUAD mode. Signed-off-by: Vignesh R Tested-by: Marek Vasut Acked-by: Marek Vasut Reviewed-by: Jagan Teki

spi: cadence_qspi_apb: Support 32 bit AHB address

2016-07-09T14:46:32Z

AHB address can be as long as 32 bit, hence remove the CQSPI_REG_INDIRECTRDSTARTADDR mask. Since AHB address is passed from DT and read as u32 value, it anyway does not make sense to mask upper bits. Signed-off-by: Vignesh R Tested-by: Marek Vasut Acked-by: Marek Vasut Reviewed-by: Jagan Teki

spi: davinci_spi: Convert to driver to adapt to DM

2016-07-09T14:46:30Z

Convert davinci_spi driver so that it complies with SPI DM framework. Signed-off-by: Vignesh R Reviewed-by: Simon Glass Reviewed-by: Jagan Teki

spi: spi-uclass: fix typo in debug output

2016-07-06T07:10:32Z

Signed-off-by: Anatolij Gustschin Reviewed-by: Jagan Teki

driver: qspi: correct QSPI disable CS reset value

2016-07-01T21:42:53Z

Correcting QSPI disable/unselect CS reset value. CTRL_CORE_CONTROL_IO_2: QSPI_MEMMAPPED_CS[10:8] This is not causing any issue, but its better to untouch the reserved bits. Praneeth Bajjuri Signed-off-by: Ravi Babu

clk: convert API to match reset/mailbox style

2016-06-19T23:05:55Z

The following changes are made to the clock API: * The concept of "clocks" and "peripheral clocks" are unified; each clock provider now implements a single set of clocks. This provides a simpler conceptual interface to clients, and better aligns with device tree clock bindings. * Clocks are now identified with a single "struct clk", rather than requiring clients to store the clock provider device and clock identity values separately. For simple clock consumers, this isolates clients from internal details of the clock API. * clk.h is split so it only contains the client/consumer API, whereas clk-uclass.h contains the provider API. This aligns with the recently added reset and mailbox APIs. * clk_ops .of_xlate(), .request(), and .free() are added so providers can customize these operations if needed. This also aligns with the recently added reset and mailbox APIs. * clk_disable() is added. * All users of the current clock APIs are updated. * Sandbox clock tests are updated to exercise clock lookup via DT, and clock enable/disable. * rkclk_get_clk() is removed and replaced with standard APIs. Buildman shows no clock-related errors for any board for which buildman can download a toolchain. test/py passes for sandbox (which invokes the dm clk test amongst others). Signed-off-by: Stephen Warren Acked-by: Simon Glass

spi: pic32_spi: add SPI master driver for PIC32 SoC.

2016-06-10T10:31:12Z

This driver implements SPI protocol in master mode to communicate with the SPI device connected on SPI bus. It handles /CS explicitly by controlling respective pin as gpio ('cs-gpios' property in dt node) and uses PIO mode for SPI transaction. It is configurable based on driver-model only. Cc: Jagan Teki Signed-off-by: Purna Chandra Mandal Reviewed-by: Daniel Schwierzeck

Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq

2016-05-24T17:42:03Z

Merge branch 'master' of git://git.denx.de/u-boot-mips

2016-05-23T15:51:37Z