u-boot.git/drivers/spi, branch v2016.09-rc2

spi: cadence_qspi_apb: Ensure baudrate doesn't exceed max value

2016-08-07T19:54:21+00:00

Ensuring the baudrate divisor value doesn't exceed the max value
in the calculation.It will be capped at max value to ensure the
correct value being written into the register.

Example of the existing bug is when calculated div = 16. After and
with the mask, the value written to register is actually 0 (register
field for baudrate divisor). With this fix, the value written is now
15 which is max value for baudrate divisor.

Signed-off-by: Chin Liang See 
Cc: Marek Vasut 
Cc: Jagan Teki 
Cc: Dinh Nguyen

driver: spi: fsl-qspi: remove compile Warnings

2016-08-02T16:45:13+00:00

Warnins log:
drivers/spi/fsl_qspi.c: In function ‘qspi_ahb_read’:
drivers/spi/fsl_qspi.c:400:16: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
  memcpy(rxbuf, (u8 *)(priv->cur_amba_base + priv->sf_addr), len);

Signed-off-by: Yunhui Cui 
Reviewed-by: York Sun

spi: ti_qspi: dra7xx: Add support to use 76.8MHz clock

2016-07-29T18:45:00+00:00

According to AM572x DM SPRS953A, QSPI bus speed can be 76.8MHz, update
the driver to use the same.

Signed-off-by: Vignesh R 
Reviewed-by: Tom Rini 
Reviewed-by: Jagan Teki 
Reviewed-by: Mugunthan V N

spi: ti_qspi: Remove delay in read path for dra7xx

2016-07-29T18:45:00+00:00

As per commit b545a98f5dc563 ("spi: ti_qspi: Add delay
for successful bulk erase) says its added to meet bulk erase timing
constraints. But bulk erase is a cmd to flash and delay in read path
does not make sense. Morever, testing on DRA74/DRA72 evm has shown that
this delay is no longer required.

Signed-off-by: Vignesh R 
Reviewed-by: Jagan Teki 
Reviewed-by: Mugunthan V N

spi: ti_qspi: Fix compiler warning when DEBUG macro is set

2016-07-29T18:45:00+00:00

clk_div is uninitialized at the beginning of ti_spi_set_speed(), move
debug() print after clk_div calculation to avoid compiler warning and to
have proper value of clk_div printed during debugging.

Signed-off-by: Vignesh R 
Reviewed-by: Jagan Teki 
Reviewed-by: Mugunthan V N

spi: ti_qspi: Fix failure on multiple READ_ID cmd

2016-07-29T18:45:00+00:00

Populating QSPI_RD_SNGL bit(0x1) in priv->cmd means that value
QSPI_INVAL (0x4) is not written to CMD field of QSPI_SPI_CMD_REG in
ti_qspi_cs_deactivate(). Therefore CS is never deactivated between
successive READ ID which results in sf probe to fail.
Fix this by not populating priv->cmd with QSPI_RD_SNGL and OR it wih
priv->cmd as required (similar to the convention followed in the
driver).

Signed-off-by: Vignesh R 
Reviewed-by: Jagan Teki 
Reviewed-by: Mugunthan V N

dm: Use dm_scan_fdt_dev() directly where possible

2016-07-27T20:15:54+00:00

Quite a few places have a bind() method which just calls dm_scan_fdt_dev().
We may as well call dm_scan_fdt_dev() directly. Update the code to do this.

Signed-off-by: Simon Glass

dm: Convert users from dm_scan_fdt_node() to dm_scan_fdt_dev()

2016-07-27T20:15:07+00:00

This new function is more convenient for callers, and handles pre-relocation
situations automatically.

Signed-off-by: Simon Glass

dm: spi: Read default speed and mode values from DT

2016-07-09T14:46:34+00:00

In case of DT boot, don't read default speed and mode for SPI from
CONFIG_*, instead read from DT node. This will make sure that boards
with multiple SPI/QSPI controllers can be probed at different
bus frequencies and SPI modes.

Signed-off-by: Vignesh R 
Reviewed-by: Simon Glass 
Reviewed-by: Mugunthan V N 
Reviewed-by: Jagan Teki

spi: cadence_quadspi: Enable QUAD mode based on DT data

2016-07-09T14:46:33+00:00

Instead of relying on CONFIG_SPI_FLASH_QUAD to be defined to enable QUAD
mode, make use of mode_rx field of dm_spi_slave_platdata to determine
whether to enable or disable QUAD mode. This is necessary to support
muliple SPI controllers where one of them may not support QUAD mode.

Signed-off-by: Vignesh R 
Tested-by: Marek Vasut 
Acked-by: Marek Vasut 
Reviewed-by: Jagan Teki