u-boot.git/drivers/spi, branch v2017.01

spi: cadence_qspi_apb: Use 32 bit indirect read transaction when possible

2017-01-04T15:38:35+00:00

According to Section 11.15.4.9.1 Indirect Read Controller of K2G SoC
TRM SPRUHY8D[1], the external master is only permitted to issue 32-bit
data interface reads until the last word of an indirect transfer
So, make sure that QSPI indirect reads are 32 bit sized except for the
final read. If the rxbuf is unaligned then use bounce buffer, so that
readsl() can be used instead of readsb() to avoid non 32-bit accesses.

[1]www.ti.com/lit/ug/spruhy8d/spruhy8d.pdf

Signed-off-by: Vignesh R 
Reviewed-by: Marek Vasut 
Reviewed-by: Jagan Teki

spi: cadence_qspi_apb: Use 32 bit indirect write transaction when possible

2017-01-04T15:38:12+00:00

According to Section 11.15.4.9.2 Indirect Write Controller of K2G SoC
TRM SPRUHY8D[1], the external master is only permitted to issue 32-bit
data interface writes until the last word of an indirect transfer
otherwise indirect writes is known to fails sometimes. So, make sure
that QSPI indirect writes are 32 bit sized except for the last write. If
the txbuf is unaligned then use bounce buffer to avoid data aborts.

So, now that the driver uses bounce_buffer, enable CONFIG_BOUNCE_BUFFER
for all boards that use Cadence QSPI driver.

[1]www.ti.com/lit/ug/spruhy8d/spruhy8d.pdf

Signed-off-by: Vignesh R 
Reviewed-by: Marek Vasut 
Reviewed-by: Jagan Teki

spi: Zap armada100_spi.c and env

2016-12-21T11:18:47+00:00

armada100_spi.c and related env is zapping becuase
of "no DM conversion".

Cc: Ajay Bhargav 
Signed-off-by: Jagan Teki

spi: Zap mpc52xx_spi.c, config and related code

2016-12-21T11:14:37+00:00

armada100_spi.c, related config options and related codes
are zapping becuase of "no DM conversion".

Cc: Werner Pfister 
Signed-off-by: Jagan Teki 
Reviewed-by: Tom Rini

spi: cadence_qspi: Move DT prop code to match layout

2016-12-15T15:57:28+00:00

Move the code to read the "sram-size" property into the other code
that reads properties from the node, rather than the SF subnode.

Signed-off-by: Phil Edworthy 
Reviewed-by: Jagan Teki

spi: cadence_qspi: Fix CS timings

2016-12-15T15:57:27+00:00

The Cadence QSPI controller has specified overheads for the various CS
times that are in addition to those programmed in to the Device Delay
register. The overheads are different for the delays.

In addition, the existing code does not handle the case when the delay
is less than a SCLK period.

This change accurately calculates the additional delays in Ref clocks.

Signed-off-by: Phil Edworthy 
Reviewed-by: Jagan Teki

spi: cadence_qspi: Remove returns from end of void functions

2016-12-15T15:57:27+00:00

Signed-off-by: Phil Edworthy 
Acked-by: Marek Vasut 
Reviewed-by: Jagan Teki

spi: cadence_qspi: Use spi mode at the point it is needed

2016-12-15T15:57:27+00:00

Instead of extracting mode settings and passing them as separate
args to another function, just pass the SPI mode as an arg.

Signed-off-by: Phil Edworthy 
Reviewed-by: Jagan Teki

spi: cadence_qspi: Clean up the #define names

2016-12-15T15:57:27+00:00

A lot of the #defines are for single bits in a register, where the
name has _MASK on the end. Since this can be used for both a mask
and the value, remove _MASK from them.

Whilst doing so, also remove the unnecessary brackets around the
constants.

Signed-off-by: Phil Edworthy 
Acked-by: Marek Vasut 
Reviewed-by: Jagan Teki

spi: cadence_qspi: Use #define for bits instead of bit shifts

2016-12-15T15:57:27+00:00

Most of the code already uses #defines for the bit value, rather
than the shift required to get the value. This changes the remaining
code over.

Whislt at it, fix the names of the "Rd Data Capture" register defs.

Signed-off-by: Phil Edworthy 
Acked-by: Marek Vasut 
Reviewed-by: Jagan Teki