u-boot.git/drivers/spi, branch v2017.01-rc2

spi: cadence_qspi: Move DT prop code to match layout

2016-12-15T15:57:28Z

Move the code to read the "sram-size" property into the other code that reads properties from the node, rather than the SF subnode. Signed-off-by: Phil Edworthy Reviewed-by: Jagan Teki

spi: cadence_qspi: Fix CS timings

2016-12-15T15:57:27Z

The Cadence QSPI controller has specified overheads for the various CS times that are in addition to those programmed in to the Device Delay register. The overheads are different for the delays. In addition, the existing code does not handle the case when the delay is less than a SCLK period. This change accurately calculates the additional delays in Ref clocks. Signed-off-by: Phil Edworthy Reviewed-by: Jagan Teki

spi: cadence_qspi: Remove returns from end of void functions

2016-12-15T15:57:27Z

Signed-off-by: Phil Edworthy Acked-by: Marek Vasut Reviewed-by: Jagan Teki

spi: cadence_qspi: Use spi mode at the point it is needed

2016-12-15T15:57:27Z

Instead of extracting mode settings and passing them as separate args to another function, just pass the SPI mode as an arg. Signed-off-by: Phil Edworthy Reviewed-by: Jagan Teki

spi: cadence_qspi: Clean up the #define names

2016-12-15T15:57:27Z

A lot of the #defines are for single bits in a register, where the name has _MASK on the end. Since this can be used for both a mask and the value, remove _MASK from them. Whilst doing so, also remove the unnecessary brackets around the constants. Signed-off-by: Phil Edworthy Acked-by: Marek Vasut Reviewed-by: Jagan Teki

spi: cadence_qspi: Use #define for bits instead of bit shifts

2016-12-15T15:57:27Z

Most of the code already uses #defines for the bit value, rather than the shift required to get the value. This changes the remaining code over. Whislt at it, fix the names of the "Rd Data Capture" register defs. Signed-off-by: Phil Edworthy Acked-by: Marek Vasut Reviewed-by: Jagan Teki

spi: cadence_qspi: Better debug information on the SPI clock rate

2016-12-15T15:57:27Z

Show what the output clock rate actually is. Signed-off-by: Phil Edworthy Acked-by: Marek Vasut Reviewed-by: Jagan Teki

spi: cadence_qspi: Fix baud rate calculation

2016-12-15T15:57:27Z

With the existing code, when the requested SPI clock rate is near to the lowest that can be achieved by the hardware (max divider of the ref clock is 32), the generated clock rate is wrong. For example, with a 50MHz ref clock, when asked for anything less than a 1.5MHz SPI clock, the code sets up the divider to generate 25MHz. This change fixes the calculation. Signed-off-by: Phil Edworthy Reviewed-by: Jagan Teki

spi: cadence_qspi: Fix clearing of pol/pha bits

2016-12-15T15:57:27Z

Or'ing together bit positions is clearly wrong. Signed-off-by: Phil Edworthy Acked-by: Marek Vasut Reviewed-by: Jagan Teki

spi: Add error checking for invalid bus widths

2016-12-15T15:38:30Z

At present an invalid bus width prints a message but does not return an error. This is the opposite of the correct behaviour. Adjust it to avoid code bloat in the common case, and avoid hard-to-debug failure in the uncommon case. Signed-off-by: Simon Glass Reviewed-by: Jagan Teki