u-boot.git/drivers/spi, branch v2017.11

spi: ich: Lock down controller settings if required

2017-10-27T07:13:47+00:00

Some Intel FSP (like Braswell) does SPI lock-down during the call
to fsp_notify(INIT_PHASE_BOOT). But before SPI lock-down is done,
it's bootloader's responsibility to configure the SPI controller's
opcode registers properly otherwise SPI controller driver doesn't
know how to communicate with the SPI flash device.

Rather than passively doing the opcode configuration, let's add a
simple DTS property "intel,spi-lock-down" and let the driver call
the opcode configuration function if required by such FSP.

Signed-off-by: Bin Meng 
Reviewed-by: Simon Glass

spi: Drop CONFIG_ATMEL_DATAFLASH_SPI

2017-10-16T13:42:51+00:00

Last user of this option went away in commit:

fdc7718999 ("board: usb_a9263: Update to support DT and DM")

Signed-off-by: Tuomas Tynkkynen 
Acked-by: Wenyou Yang

treewide: replace with error() with pr_err()

2017-10-04T15:59:44+00:00

U-Boot widely uses error() as a bit noisier variant of printf().

This macro causes name conflict with the following line in
include/linux/compiler-gcc.h:

  # define __compiletime_error(message) __attribute__((error(message)))

This prevents us from using __compiletime_error(), and makes it
difficult to fully sync BUILD_BUG macros with Linux.  (Notice
Linux's BUILD_BUG_ON_MSG is implemented by using compiletime_assert().)

Let's convert error() into now treewide-available pr_err().

Done with the help of Coccinelle, excluing tools/ directory.

The semantic patch I used is as follows:

// 
@@@@
-error
+pr_err
 (...)
// 

Signed-off-by: Masahiro Yamada 
Reviewed-by: Simon Glass 
[trini: Re-run Coccinelle]
Signed-off-by: Tom Rini

spi: davinci_spi: Add da830-spi support for DM

2017-09-29T14:52:20+00:00

The DM support is already in the driver, so add
da830-spi to the compatible list.

Reviewed-by: Jagan Teki 
Signed-off-by: Adam Ford

spi: fsl_qspi: Copy 16 byte aligned data in TX FIFO

2017-09-25T10:15:15+00:00

In some of the QSPI controller version, there must be atleast
128bit data available in TX FIFO for any pop operation otherwise
error bit will be set. The code will not make any behavior change
for previous controller as the transfer data size in ipcr register
is still the same.

Patch is tested on LS1046A which do not require 16 bytes aligned and
LS1088A which require 16 bytes aligned data in TX FIFO

Signed-off-by: Suresh Gupta 
Signed-off-by: Anupam Kumar 
Reviewed-by: Jagan Teki

spi: fsl_qspi: Add controller busy check before new spi operation

2017-09-25T07:19:56+00:00

It is recommended to check either controller is free to take
new spi action. The IP_ACC and AHB_ACC bits indicates that
the controller is busy in IP or AHB mode respectively.
And the BUSY bit indicates that controller is currently
busy handling a transaction to an external flash device

Signed-off-by: Suresh Gupta 
Reviewed-by: Jagan Teki

spi: mxc_spi: support driver model

2017-09-25T07:17:59+00:00

Add driver model support for mxc spi driver.
Most functions are restructured to be reused by DM and non-DM.
Tested on mx6slevk/mx6qsabresd board.

Signed-off-by: Peng Fan 
Reviewed-by: Jagan Teki 
Reviewed-by: Stefano Babic

nds32: spi: Support spi dm driver.

2017-09-21T02:30:22+00:00

Support spi driver and can detect MX25U1635E flash on AE3XX board.

Verification:

sf probe 0:0 50000000 0
spi_flash_std_probe(sf_Probr.c)
	spi_flash_probe_slave(sf_Probr.c)
	SF: Detected mx25u1635e with page size 256 Bytes, erase size 4 KiB, total 2 MiB
	NDS32 # sf test 0x100000 0x1000
	SPI flash test:
	0 erase: 34 ticks, 117 KiB/s 0.936 Mbps
	1 check: 15 ticks, 266 KiB/s 2.128 Mbps
	2 write: 21 ticks, 190 KiB/s 1.520 Mbps
	3 read: 11 ticks, 363 KiB/s 2.904 Mbps
	Test passed
	0 erase: 34 ticks, 117 KiB/s 0.936 Mbps
	1 check: 15 ticks, 266 KiB/s 2.128 Mbps
	2 write: 21 ticks, 190 KiB/s 1.520 Mbps
	3 read: 11 ticks, 363 KiB/s 2.904 Mbps

Signed-off-by: rick

rockchip: spi: Convert to livetree

2017-09-18T18:40:35+00:00

Update the Rockchip SPI driver to support a live device tree.

Signed-off-by: Philipp Tomsich 
Reviewed-by: Simon Glass 
Reviewed-by: Jagan Teki 
Acked-by: Philipp Tomsich

x86: ich-spi: Clear atomic preop only when SPI settings are not locked

2017-09-02T15:35:55+00:00

The atomic preop register can only be written when SPI settings are
not locked, otherwise it's read-only.

Signed-off-by: Bin Meng 
Reviewed-by: Stefan Roese