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<title>u-boot.git/drivers/spi, branch v2018.01</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>cosmetic: atcspi200: Rename function name as atcspi200</title>
<updated>2017-11-30T01:45:21+00:00</updated>
<author>
<name>Rick Chen</name>
<email>rick@andestech.com</email>
</author>
<published>2017-11-23T06:17:35+00:00</published>
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<id>6720e4ae7a01afa93b99a8f62b0cc98fe01abc9b</id>
<content type='text'>
Integrate function and struct name from ae3xx to
atcspi200 will be more reasonable.

Signed-off-by: Rick Chen &lt;rick@andestech.com&gt;
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<pre>
Integrate function and struct name from ae3xx to
atcspi200 will be more reasonable.

Signed-off-by: Rick Chen &lt;rick@andestech.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>spi: nds_ae3xx: Rename nds_ae3xx_spi as atcspi200_spi</title>
<updated>2017-11-30T01:44:09+00:00</updated>
<author>
<name>Rick Chen</name>
<email>rick@andestech.com</email>
</author>
<published>2017-11-23T06:19:36+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=41bbb8b333a6977cd28d31c58a5a209001ce5056'/>
<id>41bbb8b333a6977cd28d31c58a5a209001ce5056</id>
<content type='text'>
atcspi200 is Andestech spi ip which is embedded in
AE3XX and AE250 platforms. So rename as atcspi200
will be more reasonable to be used in different
platforms.

Signed-off-by: Rick Chen &lt;rick@andestech.com&gt;
</content>
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<pre>
atcspi200 is Andestech spi ip which is embedded in
AE3XX and AE250 platforms. So rename as atcspi200
will be more reasonable to be used in different
platforms.

Signed-off-by: Rick Chen &lt;rick@andestech.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>rockchip: spi: the symbol for Hertz is Hz</title>
<updated>2017-11-21T22:57:23+00:00</updated>
<author>
<name>Heinrich Schuchardt</name>
<email>xypron.glpk@gmx.de</email>
</author>
<published>2017-11-12T19:59:44+00:00</published>
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<id>11f12c17d72499292f6e219ebbf8062faedcc5bb</id>
<content type='text'>
fix typo

Signed-off-by: Heinrich Schuchardt &lt;xypron.glpk@gmx.de&gt;
Acked-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
Reviewed-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
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<pre>
fix typo

Signed-off-by: Heinrich Schuchardt &lt;xypron.glpk@gmx.de&gt;
Acked-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
Reviewed-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>omap3: spi: the symbol for Hertz is Hz</title>
<updated>2017-11-21T01:18:40+00:00</updated>
<author>
<name>Heinrich Schuchardt</name>
<email>xypron.glpk@gmx.de</email>
</author>
<published>2017-11-12T20:02:52+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=042de609ed49cfc41afb13639850c7b01079a527'/>
<id>042de609ed49cfc41afb13639850c7b01079a527</id>
<content type='text'>
fix typo

Signed-off-by: Heinrich Schuchardt &lt;xypron.glpk@gmx.de&gt;
</content>
<content type='xhtml'>
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<pre>
fix typo

Signed-off-by: Heinrich Schuchardt &lt;xypron.glpk@gmx.de&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>spi: ich: Lock down controller settings if required</title>
<updated>2017-10-27T07:13:47+00:00</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2017-10-19T01:20:57+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=ab20107468de5bf6b9affa93b17f2284cc838b5b'/>
<id>ab20107468de5bf6b9affa93b17f2284cc838b5b</id>
<content type='text'>
Some Intel FSP (like Braswell) does SPI lock-down during the call
to fsp_notify(INIT_PHASE_BOOT). But before SPI lock-down is done,
it's bootloader's responsibility to configure the SPI controller's
opcode registers properly otherwise SPI controller driver doesn't
know how to communicate with the SPI flash device.

Rather than passively doing the opcode configuration, let's add a
simple DTS property "intel,spi-lock-down" and let the driver call
the opcode configuration function if required by such FSP.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
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<pre>
Some Intel FSP (like Braswell) does SPI lock-down during the call
to fsp_notify(INIT_PHASE_BOOT). But before SPI lock-down is done,
it's bootloader's responsibility to configure the SPI controller's
opcode registers properly otherwise SPI controller driver doesn't
know how to communicate with the SPI flash device.

Rather than passively doing the opcode configuration, let's add a
simple DTS property "intel,spi-lock-down" and let the driver call
the opcode configuration function if required by such FSP.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>spi: Drop CONFIG_ATMEL_DATAFLASH_SPI</title>
<updated>2017-10-16T13:42:51+00:00</updated>
<author>
<name>Tuomas Tynkkynen</name>
<email>tuomas.tynkkynen@iki.fi</email>
</author>
<published>2017-10-10T18:59:41+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=95688de311e238ccfba21c50b1b67ceffbdc7fc5'/>
<id>95688de311e238ccfba21c50b1b67ceffbdc7fc5</id>
<content type='text'>
Last user of this option went away in commit:

fdc7718999 ("board: usb_a9263: Update to support DT and DM")

Signed-off-by: Tuomas Tynkkynen &lt;tuomas.tynkkynen@iki.fi&gt;
Acked-by: Wenyou Yang &lt;wenyou.yang@microchip.com&gt;
</content>
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<pre>
Last user of this option went away in commit:

fdc7718999 ("board: usb_a9263: Update to support DT and DM")

Signed-off-by: Tuomas Tynkkynen &lt;tuomas.tynkkynen@iki.fi&gt;
Acked-by: Wenyou Yang &lt;wenyou.yang@microchip.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>treewide: replace with error() with pr_err()</title>
<updated>2017-10-04T15:59:44+00:00</updated>
<author>
<name>Masahiro Yamada</name>
<email>yamada.masahiro@socionext.com</email>
</author>
<published>2017-09-16T05:10:41+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=9b643e312d528f291966c1f30b0d90bf3b1d43dc'/>
<id>9b643e312d528f291966c1f30b0d90bf3b1d43dc</id>
<content type='text'>
U-Boot widely uses error() as a bit noisier variant of printf().

This macro causes name conflict with the following line in
include/linux/compiler-gcc.h:

  # define __compiletime_error(message) __attribute__((error(message)))

This prevents us from using __compiletime_error(), and makes it
difficult to fully sync BUILD_BUG macros with Linux.  (Notice
Linux's BUILD_BUG_ON_MSG is implemented by using compiletime_assert().)

Let's convert error() into now treewide-available pr_err().

Done with the help of Coccinelle, excluing tools/ directory.

The semantic patch I used is as follows:

// &lt;smpl&gt;
@@@@
-error
+pr_err
 (...)
// &lt;/smpl&gt;

Signed-off-by: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
[trini: Re-run Coccinelle]
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
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<pre>
U-Boot widely uses error() as a bit noisier variant of printf().

This macro causes name conflict with the following line in
include/linux/compiler-gcc.h:

  # define __compiletime_error(message) __attribute__((error(message)))

This prevents us from using __compiletime_error(), and makes it
difficult to fully sync BUILD_BUG macros with Linux.  (Notice
Linux's BUILD_BUG_ON_MSG is implemented by using compiletime_assert().)

Let's convert error() into now treewide-available pr_err().

Done with the help of Coccinelle, excluing tools/ directory.

The semantic patch I used is as follows:

// &lt;smpl&gt;
@@@@
-error
+pr_err
 (...)
// &lt;/smpl&gt;

Signed-off-by: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
[trini: Re-run Coccinelle]
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>spi: davinci_spi: Add da830-spi support for DM</title>
<updated>2017-09-29T14:52:20+00:00</updated>
<author>
<name>Adam Ford</name>
<email>aford173@gmail.com</email>
</author>
<published>2017-09-18T01:43:45+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=ab0ac272421c4b72c7a78db32ad709e23cab1eea'/>
<id>ab0ac272421c4b72c7a78db32ad709e23cab1eea</id>
<content type='text'>
The DM support is already in the driver, so add
da830-spi to the compatible list.

Reviewed-by: Jagan Teki &lt;jagan@openedev.com&gt;
Signed-off-by: Adam Ford &lt;aford173@gmail.com&gt;
</content>
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<pre>
The DM support is already in the driver, so add
da830-spi to the compatible list.

Reviewed-by: Jagan Teki &lt;jagan@openedev.com&gt;
Signed-off-by: Adam Ford &lt;aford173@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>spi: fsl_qspi: Copy 16 byte aligned data in TX FIFO</title>
<updated>2017-09-25T10:15:15+00:00</updated>
<author>
<name>Suresh Gupta</name>
<email>suresh.gupta@nxp.com</email>
</author>
<published>2017-06-05T09:07:20+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=10509987285515b0a969c39ef7374fea3545851b'/>
<id>10509987285515b0a969c39ef7374fea3545851b</id>
<content type='text'>
In some of the QSPI controller version, there must be atleast
128bit data available in TX FIFO for any pop operation otherwise
error bit will be set. The code will not make any behavior change
for previous controller as the transfer data size in ipcr register
is still the same.

Patch is tested on LS1046A which do not require 16 bytes aligned and
LS1088A which require 16 bytes aligned data in TX FIFO

Signed-off-by: Suresh Gupta &lt;suresh.gupta@nxp.com&gt;
Signed-off-by: Anupam Kumar &lt;anupam.kumar_1@nxp.com&gt;
Reviewed-by: Jagan Teki &lt;jagan@openedev.com&gt;
</content>
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<pre>
In some of the QSPI controller version, there must be atleast
128bit data available in TX FIFO for any pop operation otherwise
error bit will be set. The code will not make any behavior change
for previous controller as the transfer data size in ipcr register
is still the same.

Patch is tested on LS1046A which do not require 16 bytes aligned and
LS1088A which require 16 bytes aligned data in TX FIFO

Signed-off-by: Suresh Gupta &lt;suresh.gupta@nxp.com&gt;
Signed-off-by: Anupam Kumar &lt;anupam.kumar_1@nxp.com&gt;
Reviewed-by: Jagan Teki &lt;jagan@openedev.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>spi: fsl_qspi: Add controller busy check before new spi operation</title>
<updated>2017-09-25T07:19:56+00:00</updated>
<author>
<name>Suresh Gupta</name>
<email>suresh.gupta@nxp.com</email>
</author>
<published>2017-08-30T14:36:33+00:00</published>
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<id>1c631da459a82f4f82a063f5b4ff339ca5384d11</id>
<content type='text'>
It is recommended to check either controller is free to take
new spi action. The IP_ACC and AHB_ACC bits indicates that
the controller is busy in IP or AHB mode respectively.
And the BUSY bit indicates that controller is currently
busy handling a transaction to an external flash device

Signed-off-by: Suresh Gupta &lt;suresh.gupta@nxp.com&gt;
Reviewed-by: Jagan Teki &lt;jagan@openedev.com&gt;
</content>
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<pre>
It is recommended to check either controller is free to take
new spi action. The IP_ACC and AHB_ACC bits indicates that
the controller is busy in IP or AHB mode respectively.
And the BUSY bit indicates that controller is currently
busy handling a transaction to an external flash device

Signed-off-by: Suresh Gupta &lt;suresh.gupta@nxp.com&gt;
Reviewed-by: Jagan Teki &lt;jagan@openedev.com&gt;
</pre>
</div>
</content>
</entry>
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