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<title>u-boot.git/drivers/spi, branch v2018.03-rc2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/spi?h=v2018.03-rc2</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/drivers/spi?h=v2018.03-rc2'/>
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<updated>2018-02-08T03:06:18Z</updated>
<entry>
<title>atcspi200: avoid possible NULL dereference</title>
<updated>2018-02-08T03:06:18Z</updated>
<author>
<name>Heinrich Schuchardt</name>
<email>xypron.glpk@gmx.de</email>
</author>
<published>2018-01-31T00:05:54Z</published>
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<id>urn:sha1:923837e159c5886be38c7a83a2d6bc489b35c1f4</id>
<content type='text'>
Check if ns before and not after dereferencing it.

Indicated by cppcheck.

Signed-off-by: Heinrich Schuchardt &lt;xypron.glpk@gmx.de&gt;
</content>
</entry>
<entry>
<title>Merge git://git.denx.de/u-boot-spi</title>
<updated>2018-01-26T12:46:34Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2018-01-26T12:46:34Z</published>
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<id>urn:sha1:1d12a7c8cd4e58d5c3989bc239d5fa9577079dfd</id>
<content type='text'>
</content>
</entry>
<entry>
<title>DW SPI: Get clock value from Device Tree</title>
<updated>2018-01-26T05:56:16Z</updated>
<author>
<name>Eugeniy Paltsev</name>
<email>Eugeniy.Paltsev@synopsys.com</email>
</author>
<published>2017-12-28T12:09:03Z</published>
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<id>urn:sha1:58c125b9e2b232ce73ed7b24ba7b1ca5ff41c5bd</id>
<content type='text'>
Add option to set spi controller clock frequency via device tree
using standard clock bindings.

Define dw_spi_get_clk function as 'weak' as some targets
(like SOCFPGA_GEN5 and SOCFPGA_ARRIA10) don't use standard clock API
and implement dw_spi_get_clk their own way in their clock manager.

Get rid of clock_manager.h include as we don't use
cm_get_spi_controller_clk_hz function anymore. (we use redefined
dw_spi_get_clk in SOCFPGA clock managers instead)

Reviewed-by: Marek Vasut &lt;marex@denx.de&gt;
Signed-off-by: Eugeniy Paltsev &lt;Eugeniy.Paltsev@synopsys.com&gt;
Reviewed-by: Jagan Teki &lt;jagan@openedev.com&gt;
</content>
</entry>
<entry>
<title>spi: cadence_qspi_apb: Make flash writes 32 bit aligned</title>
<updated>2018-01-24T06:41:36Z</updated>
<author>
<name>Vignesh R</name>
<email>vigneshr@ti.com</email>
</author>
<published>2018-01-24T05:14:07Z</published>
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<id>urn:sha1:aaa21d3ffc023623a3a8247e5fa25d0db2bfb630</id>
<content type='text'>
Make flash writes 32 bit aligned by using bounce buffers to deal with
non 32 bit aligned buffers.
This is required because as per TI K2G TRM[1], the external master is
only permitted to issue 32-bit data interface writes until the last word
of an indirect transfer. Otherwise indirect writes is known to fail
sometimes.

[1] http://www.ti.com/lit/ug/spruhy8g/spruhy8g.pdf

Signed-off-by: Vignesh R &lt;vigneshr@ti.com&gt;
Acked-by: Marek Vasut &lt;marex@denx.de&gt;
Acked-by: Simon Goldschmidt &lt;sgoldschmidt@de.pepperl-fuchs.com&gt;
Reviewed-by: Jason Rush &lt;jarush@gmail.com&gt;
Acked-by: Jason Rush &lt;jarush@gmail.com&gt;
Reviewed-by: Jagan Teki &lt;jagan@openedev.com&gt;
</content>
</entry>
<entry>
<title>Revert "spi: cadence_qspi_apb: Use 32 bit indirect write transaction when possible"</title>
<updated>2018-01-24T06:41:36Z</updated>
<author>
<name>Vignesh R</name>
<email>vigneshr@ti.com</email>
</author>
<published>2018-01-24T05:14:06Z</published>
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<id>urn:sha1:a743e2ba3837db5e8499b03f0f57c3610d03a570</id>
<content type='text'>
This reverts commit 57897c13de03ac0136d64641a3eab526c6810387.

Using bounce_buf.c to handle non-DMA alignment problems is bad as
bounce_buf.c does cache manipulations which is not required. Therefore
revert this patch in favour of local bounce buffer solution in the next
patch.

Signed-off-by: Vignesh R &lt;vigneshr@ti.com&gt;
Acked-by: Marek Vasut &lt;marex@denx.de&gt;
Acked-by: Simon Goldschmidt &lt;sgoldschmidt@de.pepperl-fuchs.com&gt;
Reviewed-by: Jason Rush &lt;jarush@gmail.com&gt;
Acked-by: Jason Rush &lt;jarush@gmail.com&gt;
Reviewed-by: Jagan Teki &lt;jagan@openedev.com&gt;
</content>
</entry>
<entry>
<title>Revert "spi: cadence_qspi_apb: Use 32 bit indirect read transaction when possible"</title>
<updated>2018-01-24T06:41:36Z</updated>
<author>
<name>Goldschmidt Simon</name>
<email>sgoldschmidt@de.pepperl-fuchs.com</email>
</author>
<published>2018-01-24T05:14:05Z</published>
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<id>urn:sha1:948ad4f07598a729a0de523ed3d779115b2fa2f2</id>
<content type='text'>
This reverts commit b63b46313ed29e9b0c36b3d6b9407f6eade40c8f.

This commit changed cadence_qspi_apb to use bouncebuf.c, which invalidates
the data cache after reading. This is meant for dma transfers only and
breaks the cadence_qspi driver which copies via cpu only: data that is
copied by the cpu is in cache only and the cache invalidation at the end
throws away this data.

Signed-off-by: Simon Goldschmidt &lt;sgoldschmidt@de.pepperl-fuchs.com&gt;
Signed-off-by: Vignesh R &lt;vigneshr@ti.com&gt;
Acked-by: Marek Vasut &lt;marex@denx.de&gt;
Reviewed-by: Jason Rush &lt;jarush@gmail.com&gt;
Acked-by: Jason Rush &lt;jarush@gmail.com&gt;
Reviewed-by: Jagan Teki &lt;jagan@openedev.com&gt;
</content>
</entry>
<entry>
<title>spi: cadence_spi: Sync DT bindings with Linux</title>
<updated>2018-01-24T06:37:50Z</updated>
<author>
<name>Jason Rush</name>
<email>jarush@gmail.com</email>
</author>
<published>2018-01-23T23:13:09Z</published>
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<id>urn:sha1:15a70a5da33229de884f60684a562ea60fe505b2</id>
<content type='text'>
Adopt the Linux DT bindings. This also fixes an issue
with the indaddrtrig register on the Cadence QSPI
device being programmed with the wrong value for the
socfpga arch.

Tested on TI K2G platform:
Tested-by: Vignesh R &lt;vigneshr@ti.com&gt;

Tested on a socfpga-cyclonev board:
Tested-by: Simon Goldschmidt &lt;sgoldschmidt@de.pepperl-fuchs.com&gt;

Signed-off-by: Jason Rush &lt;jarush@gmail.com&gt;
Reviewed-by: Jagan Teki &lt;jagan@openedev.com&gt;
Acked-by: Simon Goldschmidt &lt;sgoldschmidt@de.pepperl-fuchs.com&gt;
Acked-by: Marek Vasut &lt;marex@denx.de&gt;
</content>
</entry>
<entry>
<title>spi: kirkwood_spi: implement workaround for FE-9144572</title>
<updated>2018-01-24T06:34:08Z</updated>
<author>
<name>Chris Packham</name>
<email>judge.packham@gmail.com</email>
</author>
<published>2018-01-22T09:44:20Z</published>
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<id>urn:sha1:df16881cea50a787c37591bd2168c8ea656217bd</id>
<content type='text'>
Erratum NO. FE-9144572: The device SPI interface supports frequencies of
up to 50 MHz.  However, due to this erratum, when the device core clock
is 250 MHz and the SPI interfaces is configured for 50MHz SPI clock and
CPOL=CPHA=1 there might occur data corruption on reads from the SPI
device.

Implement the workaround by setting the TMISO_SAMPLE value to 0x2
in the timing1 register.

Signed-off-by: Chris Packham &lt;judge.packham@gmail.com&gt;
Reviewed-by: Stefan Roese &lt;sr@denx.de&gt;
Reviewed-by: Jagan Teki &lt;jagan@openedev.com&gt;
</content>
</entry>
<entry>
<title>spi: spi-uclass: Fix style violations</title>
<updated>2018-01-24T06:34:08Z</updated>
<author>
<name>Mario Six</name>
<email>mario.six@gdsys.cc</email>
</author>
<published>2018-01-15T10:08:41Z</published>
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<id>urn:sha1:24fc1ec2ee71cd852e556f90bd352cc809ddeef9</id>
<content type='text'>
Remove a superfluous newline, and reduce the scope of a variable.

Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Jagan Teki &lt;jagan@openedev.com&gt;
Signed-off-by: Mario Six &lt;mario.six@gdsys.cc&gt;
</content>
</entry>
<entry>
<title>spi: Remove spi_setup_slave_fdt</title>
<updated>2018-01-24T06:34:07Z</updated>
<author>
<name>Mario Six</name>
<email>mario.six@gdsys.cc</email>
</author>
<published>2018-01-15T10:08:38Z</published>
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<id>urn:sha1:184fa1c8da54d3c5305b3e1975e284e01de68bea</id>
<content type='text'>
A previous patch removed the spi_flash_probe_fdt function, which
contained the last call of the spi_setup_slave_fdt function, which is
now equally obsolete.

This patch removes the function.

Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Jagan Teki &lt;jagan@openedev.com&gt;
Signed-off-by: Mario Six &lt;mario.six@gdsys.cc&gt;
</content>
</entry>
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