u-boot.git/drivers/spi, branch v2018.11

arm64: versal: Add support for new Xilinx Versal ACAPs

2018-10-16T14:53:21+00:00

Xilinx is introducing Versal, an adaptive compute acceleration platform
(ACAP), built on 7nm FinFET process technology. Versal ACAPs combine
Scalar Processing Engines, Adaptable Hardware Engines, and Intelligent
Engines with leading-edge memory and interfacing technologies to deliver
powerful heterogeneous acceleration for any application. The Versal AI
Core series has five devices, offering 128 to 400 AI Engines. The series
includes dual-core Arm Cortex™-A72 application processors, dual-core Arm
Cortex-R5 real-time processors, 256KB of on-chip memory with ECC, more
than 1,900 DSP engines optimized for high-precision floating point with
low latency.

The patch is adding necessary infrastructure in place without enabling
platform which is done in separate patch.

Signed-off-by: Michal Simek

Merge branch 'master' of git://git.denx.de/u-boot-spi

2018-10-12T15:54:13+00:00

spi: davinci: Add platdata support

2018-10-10T06:05:06+00:00

Davanci spi driver has DM support already, this patch
add support for platdata so-that SPL can use it for
low foot-print.

Signed-off-by: Jagan Teki 
Tested-by: Adam Ford

dm: spi: Add logging of some return values

2018-10-09T10:40:27+00:00

When SPI flash operations fail it is helpful to be able to see the error
codes and where they are generated. Add logging to capture this
information for read operations.

Signed-off-by: Simon Glass

sandbox: spi: Add more logging

2018-10-09T10:40:27+00:00

Add logging to aid debugging features in these drivers. Also drop some
code in sandbox_spi_xfer() which is not used.

Signed-off-by: Simon Glass

spi: Add SPI driver for MT76xx SoCs

2018-10-04T12:57:28+00:00

This patch adds the SPI driver for the MediaTek MT7688 SoC (and
derivates). Its been tested on the LinkIt Smart 7688 and the Gardena
Smart Gateway with and SPI NOR on CS0 and on the Gardena Smart
Gateway additionally with an SPI NAND on CS1.

Note that the SPI controller only supports a max transfer size of 32
bytes. This driver implementes a workaround to enable bigger xfer
sizes to speed up the transfer especially for the SPI NAND support.

Signed-off-by: Stefan Roese 
Cc: Jagan Teki 
Cc: Daniel Schwierzeck 
Cc: Piotr Dymacz 
Reviewed-by: Jagan Teki 
Reviewed-by: Daniel Schwierzeck

Merge branch 'master' of git://git.denx.de/u-boot-spi

2018-10-02T21:01:46+00:00

This is the PR for SPI-NAND changes along with few spi changes.

[trini: Re-sync changes for ls1012afrwy_qspi*_defconfig]
Signed-off-by: Tom Rini

spi: sh_qspi: Add DM support to SH QSPI driver

2018-10-02T16:44:59+00:00

Add DM support to the SH QSPI driver while retaining non-DM support.
The later is required as this driver is used in SPL which has a size
limitation of 16 kiB.

Signed-off-by: Marek Vasut 
Cc: Nobuhiro Iwamatsu 
[jagan: use proper commit head]
Reviewed-by: Jagan Teki

driver/spi: fsl_qspi: Remove non-DM stuff

2018-10-02T16:43:58+00:00

Convert fsl_qspi.c to complete DM mode.

Signed-off-by: Ashish Kumar 
Tested-by: Rajat Srivastava 
Tested-by: Ye Li 
Reviewed-by: Jagan Teki

spi: designware_spi: Add reset ctrl to driver

2018-10-02T16:43:58+00:00

Add code to reset all reset signals as in SPI DT node. A reset property
is an optional feature, so only print out a warning and do not fail if a
reset property is not present.

If a reset property is discovered, then use it to deassert, thus
bringing the IP out of reset.

Release reset when _remove().

Signed-off-by: Ley Foon Tan 
Acked-by: Marek Vasut 
Reviewed-by: Jagan Teki