u-boot.git/drivers/spi, branch v2020.01

spi: rk: Limit transfers to (64K - 1) bytes

2019-12-27T12:17:26+00:00

The Rockchip SPI controller's length register only supports 16-bits,
yielding a maximum length of 64KiB (the CTRLR1 register holds "length -
1"). Trying to transfer more than that (e.g., with a large SPI flash
read) will cause the driver to hang.

Now, it seems that while theoretically we should be able to program
CTRLR1 with 0xffff, and get a 64KiB transfer, but that also seems to
cause the core to choke, so stick with a maximum of 64K - 1 bytes --
i.e., 0xffff.

Note, that the size is further divided into 'minus 1' while writing
into CTRLR1.

This change fixed two different read issues,

1. sf read failure when with > 0x10000

2. Boot from SPI flash failed during spi_flash_read call in
   common/spl/spl_spi.c

Observed and Tested in
- Rockpro64 with Gigadevice flash
- ROC-RK3399-PC with Winbond flash

Signed-off-by: Jagan Teki 
Reviewed-by: Kever Yang

common: Move ARM cache operations out of common.h

2019-12-02T23:24:58+00:00

These functions are CPU-related and do not use driver model. Move them to
cpu_func.h

Signed-off-by: Simon Glass 
Reviewed-by: Daniel Schwierzeck 
Reviewed-by: Tom Rini

common: Move get_ticks() function out of common.h

2019-12-02T23:23:13+00:00

This function belongs in time.h so move it over and add a comment.

Signed-off-by: Simon Glass 
Reviewed-by: Tom Rini

spi: cadence_qspi: support DM_CLK

2019-11-20T22:46:11+00:00

Support loading clk speed via DM instead of requiring ad-hoc code.

Signed-off-by: Simon Goldschmidt

configs: spi: Add the SPI_FLASH_BAR for ESPI

2019-11-08T11:02:08+00:00

Add the SPI_FLASH_BAR for the ESPI controller of FSL, this entry
is missed by
commit 6d8251783641 ("configs: Don't use SPI_FLASH_BAR as default")

Signed-off-by: Xiaowei Bao 
Signed-off-by: Priyanka Jain

spi: Add support for memory-mapped flash

2019-11-02T23:20:26+00:00

On x86 platforms the SPI flash can be mapped into memory so that the
contents can be read with normal memory accesses.

Add a new SPI method to find the location of the SPI flash in memory. This
differs from the existing device-tree "memory-map" mechanism in that the
location can be discovered at run-time.

Signed-off-by: Simon Glass 
Reviewed-by: Bin Meng

Merge https://gitlab.denx.de/u-boot/custodians/u-boot-sunxi

2019-10-30T13:04:52+00:00

- H6 dts(i) sync (Clément)
- H6 PIO (Icenowy)
- Fix pll1 clock calculation (Stefan)
- H6 dram, half DQ (Jernej)
- A64 OLinuXino eMMC (Sunil)

Merge tag 'mips-pull-2019-10-25' of git://git.denx.de/u-boot-mips

2019-10-26T00:07:24+00:00

- bmips: add BCRM NAND support for BCM6368, BCM6328, BCM6362 and BCM63268 SoCs
- bmips: various small fixes
- mtmips: add new drivers for clock, reset-controller and pinctrl
- mtmips: add support for high speed UART
- mtmips: update/enhance drivers for SPI and ethernet
- mtmips: add support for MMC

spi: mt7621-spi: restore default register value after each xfer

2019-10-25T15:20:44+00:00

Currently this driver uses a different way to implement the spi xfer,
by modifying some fields of two registers, which is incompatible with the
MTK's original SDK linux driver. This will cause the flash data being
damaged by the SDK driver.

This patch lets the mt7621_spi_set_cs() restore the original register
fields after cs deactivated.

Reviewed-by: Stefan Roese 
Signed-off-by: Weijie Gao

spi: mt7621-spi: remove data cache and rewrite its xfer function

2019-10-25T15:20:44+00:00

The mt7621 spi controller supports continuous generic half-duplex spi
transaction. There is no need to cache xfer data at all.

To achieve this goal, the OPADDR register must be used as the first data
to be sent. And follows the eight generic DIDO registers. But one thing
different between OPADDR and DIDO registers is OPADDR has a reversed byte
order.

With this patch, any amount of data can be read/written in a single xfer
function call.

Reviewed-by: Stefan Roese 
Signed-off-by: Weijie Gao