u-boot.git/drivers/spi, branch v2020.01-rc2

configs: spi: Add the SPI_FLASH_BAR for ESPI

2019-11-08T11:02:08Z

Add the SPI_FLASH_BAR for the ESPI controller of FSL, this entry is missed by commit 6d8251783641 ("configs: Don't use SPI_FLASH_BAR as default") Signed-off-by: Xiaowei Bao Signed-off-by: Priyanka Jain

spi: Add support for memory-mapped flash

2019-11-02T23:20:26Z

On x86 platforms the SPI flash can be mapped into memory so that the contents can be read with normal memory accesses. Add a new SPI method to find the location of the SPI flash in memory. This differs from the existing device-tree "memory-map" mechanism in that the location can be discovered at run-time. Signed-off-by: Simon Glass Reviewed-by: Bin Meng

Merge https://gitlab.denx.de/u-boot/custodians/u-boot-sunxi

2019-10-30T13:04:52Z

- H6 dts(i) sync (Clément) - H6 PIO (Icenowy) - Fix pll1 clock calculation (Stefan) - H6 dram, half DQ (Jernej) - A64 OLinuXino eMMC (Sunil)

Merge tag 'mips-pull-2019-10-25' of git://git.denx.de/u-boot-mips

2019-10-26T00:07:24Z

- bmips: add BCRM NAND support for BCM6368, BCM6328, BCM6362 and BCM63268 SoCs - bmips: various small fixes - mtmips: add new drivers for clock, reset-controller and pinctrl - mtmips: add support for high speed UART - mtmips: update/enhance drivers for SPI and ethernet - mtmips: add support for MMC

spi: mt7621-spi: restore default register value after each xfer

2019-10-25T15:20:44Z

Currently this driver uses a different way to implement the spi xfer, by modifying some fields of two registers, which is incompatible with the MTK's original SDK linux driver. This will cause the flash data being damaged by the SDK driver. This patch lets the mt7621_spi_set_cs() restore the original register fields after cs deactivated. Reviewed-by: Stefan Roese Signed-off-by: Weijie Gao

spi: mt7621-spi: remove data cache and rewrite its xfer function

2019-10-25T15:20:44Z

The mt7621 spi controller supports continuous generic half-duplex spi transaction. There is no need to cache xfer data at all. To achieve this goal, the OPADDR register must be used as the first data to be sent. And follows the eight generic DIDO registers. But one thing different between OPADDR and DIDO registers is OPADDR has a reversed byte order. With this patch, any amount of data can be read/written in a single xfer function call. Reviewed-by: Stefan Roese Signed-off-by: Weijie Gao

spi: mt7621-spi: use clock frequency from clk driver

2019-10-25T15:20:44Z

This patch lets the spi driver to use clock provided by the clk driver since the new clk-mt7628 driver provides accurate sys clock frequency. Signed-off-by: Weijie Gao

spi: designware_spi: Disable and free clock when remove driver

2019-10-24T19:18:32Z

Disable and free clock when remove driver. Signed-off-by: Ley Foon Tan Acked-by: Marek Vasut Reviewed-by: Jagan Teki

spi: Kconfig: Enable SPI_SUNXI for SUNXI

2019-10-24T19:18:31Z

SPI_SUNXI driver is fully dm-aware and the Allwinner architecture kconfig would have logic to enable the DM_SPI. So, select default spi sunxi driver for sunxi architecture. Signed-off-by: Jagan Teki

dm: spi: Change cs_info op to return -EINVAL for invalid cs num

2019-10-24T19:18:31Z

We need distinguish the following two situations in various SPI APIs: - given chip select num is invalid - given chip select num is valid, but no device is attached Currently -ENODEV is returned for both cases. For the first case, it's more reasonable to return -EINVAL instead of -ENODEV for invalid chip select numbers. Signed-off-by: Bin Meng Tested-by: Jagan Teki # SoPine Reviewed-by: Jagan Teki