u-boot.git/drivers/spi, branch v2021.01

spi: ca_sflash: Add CAxxxx SPI Flash Controller

2020-12-18T10:46:37+00:00

Add SPI Flash controller driver for Cortina Access
CAxxxx SoCs

Signed-off-by: Pengpeng Chen 
Signed-off-by: Alex Nemirovsky 
CC: Vignesh R 
CC: Tom Rini 
[jagan: rebase on master]
Signed-off-by: Jagan Teki 
Reviewed-by: Jagan Teki

spi: dw: Add mem_ops

2020-12-18T10:46:37+00:00

The designware ssi device has "broken" chip select behaviour [1], and needs
specific manipulation to use the built-in chip select. The existing fix is
to use an external GPIO for chip select, but typically the K210 has SPI3
directly connected to a flash chip with dedicated pins. This makes it
impossible to use the spi_xfer function to use spi, since the CS is
de-asserted in between calls.  This patch adds an implementation of
exec_op, which gives correct behaviour when reading/writing spi flash.

This patch also rearranges the headers to conform to U-Boot style.

[1] https://lkml.org/lkml/2015/12/23/132

Signed-off-by: Sean Anderson 
Tested-by Eugeniy Paltsev 
Reviewed-by: Jagan Teki

spi: dw: Add support for multiple CTRLR0 layouts

2020-12-18T10:46:37+00:00

CTRLR0 can have several different layouts depending on the specific device
(dw-apb-ssi vs dwc-ssi), and specific parameters set during synthesis.
Update the driver to support three specific configurations: dw-apb-ssi with
SSI_MAX_XFER_SIZE=16, dw-apb-ssi with SSI_MAX_XFER_SIZE=32, and dwc-ssi.

dw-apb-ssi is the version of the device on Altera/Intel SoCFPGAs, MSCC
SoCs, and Canaan Kendryte K210 SoCs. This is the only version this driver
supported before this change. The register layout before version 3.23a is:

|   31 .. 16  |
| other stuff |

|   15 .. 10  | 9 .. 8 | 7 .. 6 | 5 .. 4 | 3 .. 0 |
| other stuff |  TMOD  |  MODE  |  FRF   |  DFS   |

Note that DFS (Data Frame Size) is only 4 bits, limiting transfers to data
frames of 16 bits or less.

In version 3.23a, the SSI_MAX_XFER_SIZE parameter was introduced. This
parameter defaults to 16 (resulting in the same layout as prior versions),
but may also be set to 32. To allow setting longer data frame sizes, a new
DFS_32 register was introduced:

|   31 .. 21  | 20 .. 16 |
| other stuff |  DFS_32  |

|   15 .. 10  | 9 .. 8 | 7 .. 6 | 5 .. 4 |  3 .. 0   |
| other stuff |  TMOD  |  MODE  |  FRF   | all zeros |

The old DFS field no longer controls the data frame size. To detect this
layout, we try writing 0xF to DFS. If we read back 0x0, then this device
has SSI_MAX_XFER_SIZE=32.

dwc-ssi is the version of the device on Intel Keem Bay SoCs and Canaan
Kendryte K210 SoCs. The layout of ctrlr0 is:

|   31 .. 16  |
| other stuff |

|   15 .. 12  | 11 .. 10 | 9 .. 8 | 7 .. 6 | 4 .. 0 |
| other stuff |   TMOD   |  MODE  |  FRF   | DFS_32 |

The semantics of the fields have not changed since the previous version.
However, SSI_MAX_XFER_SIZE is effectively always 32.

To support these different layouts, we model our approach on the one
which the Linux kernel has taken. During probe, the driver calls an init
function stored in driver_data. This init function is responsible for
determining the layout of CTRLR0, and supplying the update_cr0 function.

The style of and information behind this commit is based on the Linux MMIO
driver for these devices. Specific reference was made to the series adding
support for Intel Keem Bay SoCs [1].

[1] https://lore.kernel.org/linux-spi/20200505130618.554-1-wan.ahmad.zainie.wan.mohamad@intel.com/

Signed-off-by: Sean Anderson 
Reviewed-by: Jagan Teki

spi: dw: Rearrange struct dw_spi_priv

2020-12-18T10:46:37+00:00

This should reduce the size of the struct, and also groups more similar
fields together.

Signed-off-by: Sean Anderson 
Tested-by Eugeniy Paltsev 
Reviewed-by: Jagan Teki

spi: dw: Remove spi_enable_chip

2020-12-18T10:46:37+00:00

This function does nothing but wrap dw_write.

Signed-off-by: Sean Anderson 
Reviewed-by: Jagan Teki

spi: dw: Rename registers to match datasheet

2020-12-18T10:46:37+00:00

A few registers had slightly different names from what is in the datasheet.

Signed-off-by: Sean Anderson 
Reviewed-by: Jagan Teki

spi: dw: Use generic function to read reg address

2020-12-18T10:46:36+00:00

Using an fdt-specific function causes problems when compiled with a live
tree.

Signed-off-by: Sean Anderson 
Tested-by Eugeniy Paltsev 
Reviewed-by: Jagan Teki

spi: dw: Rename "cs-gpio" to "cs-gpios"

2020-12-18T10:46:36+00:00

This property is named differently than other SPI drivers with the same
property, as well as the property as used in Linux.

Signed-off-by: Sean Anderson 
Tested-by Eugeniy Paltsev 
Reviewed-by: Jagan Teki

spi: dw: Convert calls to debug to dev_*

2020-12-18T10:46:36+00:00

This allows different log levels to be enabled or disabled depending on the
desired level of verbosity. In particular, it allows for general debug
information to be printed while excluding more verbose logging which may
interfere with timing.

Signed-off-by: Sean Anderson 
Reviewed-by: Jagan Teki 
Reviewed-by: Jagan Teki

spi: dw: Fix driving MOSI low while recieving

2020-12-18T10:46:36+00:00

The resting state of MOSI is high when nothing is driving it. If we drive
it low while recieving, it looks like we are transmitting 0x00 instead of
transmitting nothing. This can confuse slaves (like SD cards) which allow
new commands to be sent over MOSI while they are returning data over MISO.
The return of MOSI from 0 to 1 at the end of recieving a byte can look like
a start bit and a transmission bit to an SD card. This will cause the card
to become out-of-sync with the SPI device, as it thinks the device has
already started transmitting two bytes of a new command. The mmc-spi driver
will not detect the R1 response from the SD card, since it is sent too
early, and offset by two bits. This patch fixes transfer errors when using
SD cards with dw spi.

Signed-off-by: Sean Anderson 
Reviewed-by: Jagan Teki 
Reviewed-by: Jagan Teki