u-boot.git/drivers/spi, branch v2021.04

spi: stm32_qspi: Add WATCHDOG_RESET in _stm32_qspi_read_fifo()

2021-03-11T15:59:16Z

In case of reading large area and memory-map mode is misconfigured (memory-map size declared lower than the real size of the memory chip) watchdog can be triggered. Add WATCHDOG_RESET() in _stm32_qspi_read_fifo to fix it. Issue reproduced with stm32mp157c-ev1 board and memory map size set to 1, with following command: sf read 0xC0000000 0 0x4000000 Signed-off-by: Patrice Chotard Reviewed-by: Patrick Delaunay

spi: nxp_fspi: Fix error reporting

2021-02-26T09:39:38Z

On the i.MX8M Mini, ret = clk_set_rate() sets ret to the value of the rate the clock was able to set. When checking for errors, it only checks that it is not NULL. Since positive numbers are not errors, only check for negative numbers when handling errors. Fixes: 383fded70c4f ("spi: nxp_fspi: new driver for the FlexSPI controller") Signed-off-by: Adam Ford Reviewed-by: Pratyush Yadav Reviewed-by: Jagan Teki

spi: imx: Implement set_speed

2021-02-26T07:55:21Z

The set_speed() callback should configure the bus speed, make it so. Signed-off-by: Marek Vasut Cc: Stefano Babic Reviewed-by: Jagan Teki Reviewed-by: Bin Meng

Merge tag 'xilinx-for-v2021.04-rc3' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze

2021-02-23T15:45:55Z

Xilinx changes for v2021.04-rc3 qspi: - Support for dual/quad mode - Fix speed handling clk: - Add clock enable function for zynq/zynqmp/versal gem: - Enable clock for Versal - Fix error path - Fix mdio deregistration path fpga: - Fix buffer alignment for ZynqMP xilinx: - Fix reset reason clearing in ZynqMP - Show silicon version in SPL for Zynq/ZynqMP - Fix DTB selection for ZynqMP - Rename zc1275 to zcu1275 to match DT name

spi: zynqmp_gqspi: fix set_speed bug on multiple runs

2021-02-23T13:56:59Z

If zynqmp_qspi_set_speed() is called multiple times with the same speed, then on the second call it will skip recalculating the baud_rate_val as it assumes the speed is already configured correctly. But it will still write the baud_rate_val to the configuration register and call zynqmp_gqspi_set_tapdelay(). Because it skipped recalculating the baud_rate_val, it will use the initial value of 0 . This causes the driver to run at maximum speed which for many spi flashes is too fast and causes data corruption. Instead only write out a new baud_rate_val if we have calculated the correct baud_rate_val. This opens up another issue with the "if (speed == 0)", we don't save off the new plat->speed_hz value when setting the baud rate on the speed=0 path. Instead mimic what the Linux zynqmp gqspi driver does, and have speed==0 just use the same calculation as a normal speed. That will cause the baud_rate_val to use the slowest speed possible, which is the safest option. Signed-off-by: Brandon Maier CC: jagan@amarulasolutions.com CC: michal.simek@xilinx.com CC: Ashok Reddy Soma Signed-off-by: Michal Simek

clk: zynq: Add dummy clock enable function

2021-02-23T13:56:59Z

A lot of Xilinx drivers are checking -ENOSYS which means that clock driver doesn't have enable function. Remove this checking from drivers and create dummy enable function as was done for clk_fixed_rate driver by commit 6bf6d81c1112 ("clk: fixed_rate: add dummy enable() function"). Signed-off-by: Michal Simek

Merge branch '2021-02-02-drop-asm_global_data-when-unused'

2021-02-15T15:16:45Z

- Merge the patch to take out of

spi: fsl_qspi: apply the same settings for LS1088 as LS208x

2021-02-08T08:31:18Z

The LS1088 requires the same QUADSPI_QURIK_BASE_INTERNAL workaround as the LS208x and also has a 64 byte TX buffer. With the previous settings SPI-NAND reads over AHB were corrupted. Fixes: 91afd36f3802 ("spi: Transform the FSL QuadSPI driver to use the SPI MEM API") Signed-off-by: Mathew McBride Reviewed-by: Priyanka Jain

spi: fsl_qspi: Ensure width is respected in spi-mem operations

2021-02-08T08:31:18Z

Adapted from kernel commit b0177aca7aea From: Michael Walle Make use of a core helper to ensure the desired width is respected when calling spi-mem operators. Otherwise only the SPI controller will be matched with the flash chip, which might lead to wrong widths. Also consider the width specified by the user in the device tree. Fixes: 91afd36f38 ("spi: Add a driver for the Freescale/NXP QuadSPI controller") Signed-off-by: Michael Walle Link: https://lore.kernel.org/r/20200114154613.8195-1-michael@walle.cc Signed-off-by: Mark Brown Signed-off-by: Mathew McBride [adapt for U-Boot] Reviewed-by: Priyanka Jain

spi: zynqmp_gqspi: support dual and quad mode

2021-02-03T12:36:44Z

The dm_spi_ops.xfer() API does not support dual and quad SPI modes. It also doesn't allow the zynqmp_gqspi driver to calculate the correct number of dummy cycles for some NOR ops (as doing so also requires the buswidth). Port the zynqmp_gqspi driver to spi_controller_mem_ops, which gives us the buswidth values to correctly support all SNOR_PROTO_X_X_X commands and to properly calculate dummy cycles. Signed-off-by: Brandon Maier CC: jagan@amarulasolutions.com CC: michal.simek@xilinx.com CC: Ashok Reddy Soma Reviewed-by: Bin Meng Reviewed-by: Ashok Reddy Soma Signed-off-by: Michal Simek