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<title>u-boot.git/drivers/spi, branch v2021.10</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/spi?h=v2021.10</id>
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<updated>2021-10-04T12:51:14Z</updated>
<entry>
<title>mtd: cqspi: Fix division by zero</title>
<updated>2021-10-04T12:51:14Z</updated>
<author>
<name>Marek Vasut</name>
<email>marex@denx.de</email>
</author>
<published>2021-09-14T03:21:48Z</published>
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<id>urn:sha1:c2e0363571b124c4c543ad98d039d1eb319f1562</id>
<content type='text'>
Both dummy.nbytes and dummy.buswidth may be zero. By not checking
the later, it is possible to trigger division by zero and a crash.
This does happen with tiny SPI NOR framework in SPL. Fix this by
adding the check and returning zero dummy bytes in such a case.

Fixes: 38b0852b0ea ("spi: cadence-qspi: Add support for octal DTR flashes")
Signed-off-by: Marek Vasut &lt;marex@denx.de&gt;
Cc: Jagan Teki &lt;jagan@amarulasolutions.com&gt;
Cc: Vignesh R &lt;vigneshr@ti.com&gt;
Cc: Pratyush Yadav &lt;p.yadav@ti.com&gt;
[trini: Drop Pratyush's RB as his requested changes weren't made as
        Marek disagreed]
</content>
</entry>
<entry>
<title>pci: Drop DM_PCI</title>
<updated>2021-09-13T22:23:13Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2021-08-02T00:54:44Z</published>
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<id>urn:sha1:3232bdf0b30b057ace64f192bc55a0bed4199770</id>
<content type='text'>
This option has not effect now. Drop it, using PCI instead where needed.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>spi: zynqmp_gqspi: Fix dma alignment issue</title>
<updated>2021-09-03T07:15:01Z</updated>
<author>
<name>Ashok Reddy Soma</name>
<email>ashok.reddy.soma@xilinx.com</email>
</author>
<published>2021-08-20T13:43:17Z</published>
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<id>urn:sha1:020b353be9e6c12ebf49333a81e02d582578f560</id>
<content type='text'>
DMA is aligned to ARCH_DMA_MINALIGN(64 bytes), but as per spec, alignment
required is 4bytes only. Change DMA alignment from ARCH_DMA_MINALIGN to
GQSPI_DMA_ALIGN. Remove alignment of data length in non-exponential case.

Some minor improvements in the initialization to initialize gen_fifo
threshold and disable qspi controller while setting config register.

Signed-off-by: Ashok Reddy Soma &lt;ashok.reddy.soma@xilinx.com&gt;
Tested-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
</content>
</entry>
<entry>
<title>spi: zynqmp_gqspi: Switch genfifo start to manual mode</title>
<updated>2021-09-03T07:14:58Z</updated>
<author>
<name>Ashok Reddy Soma</name>
<email>ashok.reddy.soma@xilinx.com</email>
</author>
<published>2021-08-20T13:43:16Z</published>
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<id>urn:sha1:72022a5b2e142d4696964ffd354a01b67eb4fa72</id>
<content type='text'>
Current implementation uses auto mode for starting generic FIFO.
The recommendation from IP designers is to use manual mode, hence
change to manual start mode.

In fill genfifo first write to genfio and then trigger manual start.

Also enable and check for genfifo empty interrupt status in place of
genfifo not full interrupt.

Signed-off-by: Ashok Reddy Soma &lt;ashok.reddy.soma@xilinx.com&gt;
Tested-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
</content>
</entry>
<entry>
<title>spi: nxp_fspi: Ensure width is respected in spi-mem operations</title>
<updated>2021-08-18T10:25:15Z</updated>
<author>
<name>Michael Walle</name>
<email>michael@walle.cc</email>
</author>
<published>2021-07-26T19:35:28Z</published>
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<id>urn:sha1:364174b2d3bcad1a3ebd30c0eec9307ae5cb477a</id>
<content type='text'>
Import linux commit 007773e16a6f ("spi: nxp-fspi: Ensure width is
respected in spi-mem operations") to fix SPI access on boards which
don't have all SPI I/O lines connected to the flash.

Since commit 71025f013ccb ("mtd: spi-nor-core: Rework hwcaps selection")
u-boot figures out the capabilities by looking at spi_mem_supports_op().
The FlexSPI driver doesn't take the board layout into account. Fix that.

Fixes: 383fded70c4f ("spi: nxp_fspi: new driver for the FlexSPI controller")
Signed-off-by: Michael Walle &lt;michael@walle.cc&gt;
Reviewed-by: Pratyush Yadav &lt;p.yadav@ti.com&gt;
Reviewed-by: Priyanka Jain &lt;priyanka.jain@nxp.com&gt;
</content>
</entry>
<entry>
<title>spi: rockchip_sfc: add support for Rockchip SFC</title>
<updated>2021-08-12T01:34:11Z</updated>
<author>
<name>Chris Morgan</name>
<email>macromorgan@hotmail.com</email>
</author>
<published>2021-08-05T08:26:38Z</published>
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<id>urn:sha1:3fb08a21387b9f4f24cfd5b45f9d7f344d40fba4</id>
<content type='text'>
This patch adds support for the Rockchip serial flash controller
found on the PX30 SoC. It should work for versions 3-5 of the SFC
IP, however I am only able to test it on v3.

This is adapted from the WIP SPI-MEM driver for the SFC on mainline
Linux. Note that the main difference between this and earlier versions
of the driver is that this one does not support DMA. In testing
the performance difference (performing a dual mode read on a 128Mb
chip) is negligible. DMA, if used, must also be disabled in SPL
mode when using A-TF anyway.

Signed-off-by: Chris Morgan &lt;macromorgan@hotmail.com&gt;
Signed-off-by: Jon Lin &lt;jon.lin@rock-chips.com&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</content>
</entry>
<entry>
<title>Merge https://source.denx.de/u-boot/custodians/u-boot-spi</title>
<updated>2021-08-03T18:06:41Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2021-08-03T18:06:41Z</published>
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<id>urn:sha1:a0953b34d9d8d9309c3eabbb75746fef66b15ffe</id>
<content type='text'>
- SPI-NOR fix (Big Meng)
- XMC XM25QH64C flash (Reto Schneider)
</content>
</entry>
<entry>
<title>spi: spi-mem-nodm: Fix read data size issue</title>
<updated>2021-08-03T06:20:37Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2021-07-28T12:50:14Z</published>
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<id>urn:sha1:cb42425aa1086f2a732dd2e0614acc0c993c869d</id>
<content type='text'>
When slave drivers don't set the max_read_size, the spi-mem should
directly use data.nbytes and not limit to any size. But current
logic will limit to the max_write_size.

This commit mirrors the same changes in the dm version done in
commit 535b1fdb8e5e ("spi: spi-mem: Fix read data size issue").

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Jagan Teki &lt;jagan@amarulasolutions.com&gt;
</content>
</entry>
<entry>
<title>spi: ich: Limit slave-&gt;max_read_size</title>
<updated>2021-08-02T07:11:40Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2021-07-28T10:28:56Z</published>
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<id>urn:sha1:4dc82797585d87b61ec7b11bf54f8d302532cd55</id>
<content type='text'>
Since commit 43c145b8b3ee ("spi: ich: Correct max-size bug in ich_spi_adjust_size()")
(in v2020.04-rc1), SPI flash read no longer works with ICH SPI controller
in software sequencer mode.

ICH controller can only transfer a small number of bytes at once.
Before commit 43c145b8b3ee, the logic happens to make sure data.nbytes
is limited to slave-&gt;max_write_size but after commit 43c145b8b3ee
data.nbytes is no longer limited because slave-&gt;max_read_size is not
initialized with a valid number.

Fixes: 43c145b8b3ee ("spi: ich: Correct max-size bug in ich_spi_adjust_size()")
Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>Merge tag 'u-boot-imx-20210717' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx</title>
<updated>2021-07-17T14:52:21Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2021-07-17T14:52:21Z</published>
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<id>urn:sha1:d5dbc661c3041e910e161a95fca9e615d85730ac</id>
<content type='text'>
i.MX
----

- mx7ulp : fix  WDOG
- imx8 : Phytec
- USB3 support for i.MX8

CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/8277
</content>
</entry>
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