u-boot.git/drivers/spi, branch v2022.07

spi: nxp_fspi: Fix clock imbalance

2022-06-15T09:34:38Z

The nxp_fspi_default_setup() is only ever called from nxp_fspi_probe(), where the IP clock are initially disabled. Drop the second disabling of clock to prevent clock enable/disable imbalance reported by clock core: " clk qspi_root_clk already disabled " Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: Peng Fan Cc: Stefano Babic Reviewed-by: Peng Fan

spi: spi-uclass: Add new spi_get_bus_and_cs() implementation

2022-05-23T13:33:10Z

Move legacy spi_get_bus_and_cs() code to _spi_get_bus_and_cs(). Add new spi_get_bus_and_cs() implementation which rely on DT for speed and mode and don't need any drv_name nor dev_name parameters. This will prepare the ground for next patch. Update all callers to use _spi_get_bus_and_cs() to keep the same behavior. Signed-off-by: Patrice Chotard Cc: Marek Behun Cc: Jagan Teki Cc: Vignesh R Cc: Joe Hershberger Cc: Ramon Fried Cc: Lukasz Majewski Cc: Marek Vasut Cc: Wolfgang Denk Cc: Simon Glass Cc: Stefan Roese Cc: "Pali Rohár" Cc: Konstantin Porotchkin Cc: Igal Liberman Cc: Bin Meng Cc: Pratyush Yadav Cc: Sean Anderson Cc: Anji J Cc: Biwen Li Cc: Priyanka Jain Cc: Chaitanya Sakinam

spi: stm32_qspi: Remove SR_BUSY bit check before sending command

2022-05-19T16:54:18Z

Waiting for SR_BUSY bit when receiving a new command is not needed. SR_BUSY bit is already managed in the previous command treatment. Signed-off-by: Patrice Chotard Reviewed-by: Patrick Delaunay

spi: stm32_qspi: Always check SR_TCF flags in stm32_qspi_wait_cmd()

2022-05-19T16:54:18Z

Currently, SR_TCF flag is checked in case there is data, this criteria is not correct. SR_TCF flags is set when programmed number of bytes have been transferred to the memory device ("bytes" comprised command and data send to the SPI device). So even if there is no data, we must check SR_TCF flag. Signed-off-by: Patrice Chotard Reviewed-by: Patrick Delaunay

Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-spi

2022-05-04T13:04:43Z

- NPCM7xx FIU SPI driver (Jim Liu) - AT45DB641E dataflash (Luca Ellero)

pci: Add mask parameter to dm_pci_map_bar()

2022-05-03T22:33:29Z

Add a mask parameter to control the lookup of the PCI region from which the mapping can be made. Signed-off-by: Andrew Scull Reviewed-by: Bin Meng

pci: Map bars with offset and length

2022-05-03T19:50:46Z

Evolve dm_pci_map_bar() to include an offset and length parameter. These allow a portion of the memory to be mapped and range checks to be applied. Passing both the offset and length as zero results in the previous behaviour and this is used to migrate the previous callers. Signed-off-by: Andrew Scull Reviewed-by: Bin Meng

spi: npcm-fiu: add NPCM7xx FIU controller driver

2022-05-03T12:19:48Z

Add Nuvoton NPCM BMC Flash Interface Unit(FIU) SPI master controller driver using SPI-MEM interface. The FIU supports single, dual or quad communication interface. The FIU controller driver provides flash access in UMA(User Mode Access) mode by using an indirect address/data mechanism. the dts node is followed upstream kernel dts name. Signed-off-by: Jim Liu Signed-off-by: Stanley Chu Reviewed-by: Jagan Teki [Jagan: fixed the Kconfig, Makefile order] Signed-off-by: Jagan Teki

spi: atmel-quadspi: Fix the buswidth adjustment between spi-mem and controller

2022-04-26T06:54:41Z

Use the spi_mem_default_supports_op() core helper in order to take into account the buswidth specified by the user in device tree. Fixes: 24c8ff4684 ("spi: Add Atmel QuadSPI driver") Signed-off-by: Tudor Ambarus

spi: rockchip_sfc: Add missing include for dm/device_compat.h

2022-04-18T03:25:12Z

Add missing include for dm/device_compat.h. Without this include the SFC driver fails to compile because dev_err and dev_dbg are not defined. Signed-off-by: Chris Morgan Reviewed-by: Kever Yang