u-boot.git/drivers/spi, branch v2023.04

spi: tegra20_slink: accept any word length

2023-02-23T19:55:36Z

Original t20 slink could work with commands only fully divisible by 8. This patch removes such restriction, so commands of any bitlength now can be passed and processed. Tested-by: Andreas Westman Dorcsak # ASUS TF600T T30 Tested-by: Svyatoslav Ryhel # LG P895 T30 Tested-by: Thierry Reding # T30 and T124 Signed-off-by: Svyatoslav Ryhel Signed-off-by: Tom

Merge branch 'for-2023.04' of https://source.denx.de/u-boot/custodians/u-boot-mpc8xx

2023-02-12T20:25:09Z

- A fix for a long standing bug that has been exposed by commit 50128aeb0f8 ("cyclic: get rid of cyclic_init()") preventing 8xx boards from booting since u-boot 2023.01 - A GPIO driver for powerpc 8xx chip - Fixup for powerpc 8xx SPI driver - A new powerpc 8xx board - The two devices having that board.

spi, mpc8xx: Add support for chipselect via GPIO and fixups

2023-02-11T07:47:58Z

This patch fixes the mpc8xx SPI driver: - A stub callbacks for mode and speed, - Use chip selects defined as GPIOs, - Write proper value to disable relocation, other it fails on mpc885, - Don't modify ports setup, ports can be different from one board to another and are already set by board_early_init_r(). This patch was originally written by Charles Frey who's email address is not valid anymore as he left the company. Signed-off-by: Christophe Leroy Reviewed-by: FRANJOU Stephane

Correct SPL use of ARCH_VERSAL

2023-02-10T12:41:41Z

This converts 1 usage of this option to the non-SPL form, since there is no SPL_ARCH_VERSAL defined in Kconfig Signed-off-by: Simon Glass

Correct SPL uses of ZYNQMP_FIRMWARE

2023-02-10T12:41:41Z

This converts 2 usages of this option to the non-SPL form, since there is no SPL_ZYNQMP_FIRMWARE defined in Kconfig Signed-off-by: Simon Glass

spi: cadence_qspi: use STIG mode for small reads

2023-01-26T15:31:56Z

Fix the issue where some flash chips like cypress S25HS256T return the value of the same register over and over in DAC mode. For example in the TI K3-AM62x Processors refer [0] Technical Reference Manual there is a layer of digital logic in front of the QSPI/OSPI Drive when used in DAC mode. This is part of the Flash Subsystem (FSS) which provides access to external Flash devices. The FSS0_0_SYSCONFIG Register (Offset = 4h) has a BIT Field for OSPI_32B_DISABLE_MODE which has a Reset value = 0. This means, OSPI 32bit mode enabled by default. Thus, by default controller operates in 32 bit mode causing it to always align all data to 4 bytes from a 4byte aligned address. In some flash chips like cypress for example if we try to read some regs in DAC mode then it keeps sending the value of the first register that was requested and inorder to read the next reg, we have to stop and re-initiate a new transaction. This causes wrong register values to be read than what is desired when registers are read in DAC mode. Hence if the data.nbytes is very less then prefer STIG mode for such small reads. [0] https://www.ti.com/lit/ug/spruiv7a/spruiv7a.pdf Tested-by: Vaishnav Achath Signed-off-by: Dhruva Gole [jagan: add tab space for comments] Signed-off-by: Jagan Teki Reviewed-by: Jagan Teki

spi: cadence_qspi: setup ADDR Bits in cmd reads

2023-01-26T15:31:01Z

Setup the Addr bit field while issuing register reads in STIG mode. This is needed for example flashes like cypress define in their transaction table that to read any register there is 1 cmd byte and a few more address bytes trailing the cmd byte. Absence of addr bytes will obviously fail to read correct data from flash register that maybe requested by flash driver because the controller doesn't even specify which address of the flash register the read is being requested from. Signed-off-by: Dhruva Gole Reviewed-by: Pratyush Yadav Reviewed-by: Jagan Teki

spi: Add Socionext F_OSPI SPI flash controller driver

2023-01-26T15:23:20Z

Introduce Socionext F_OSPI controller driver. This controller is used to communicate with slave devices such as SPI flash memories. It supports 4 slave devices and up to 8-bit wide bus, but supports master mode only. This driver uses spi-mem framework for SPI flash memory access, and can only operate indirect access mode and single data rate mode. Signed-off-by: Kunihiko Hayashi Reviewed-by: Jagan Teki

drivers: spi: sh_qspi.c: Use log_warning() instead of printf()

2023-01-26T15:23:20Z

Use log_warning() instead of printf() to print out driver information Signed-off-by: Pengfei Fan Reviewed-by: Simon Glass Reviewed-by: Jagan Teki

drivers: spi: fix some typos

2023-01-26T15:23:20Z

Fix some typos in spi drivers Signed-off-by: Pengfei Fan Reviewed-by: Simon Glass Reviewed-by: Jagan Teki