u-boot.git/drivers/spi, branch v2023.07.01

drivers: spi: omap3_spi: Initialize mode for all channels

2023-06-20T20:08:13Z

At first SPI transfers, multiple chip selects can be enabled simultaneously. This is due to chip select polarity, which is not properly initialized for all channels. This patch fixes the issue. Signed-off-by: Julien Panis

Merge tag 'xilinx-for-v2023.10-rc1' of https://source.denx.de/u-boot/custodians/u-boot-microblaze into next

2023-06-12T20:42:37Z

Xilinx changes for v2023.10-rc1 global: - Use proper U-Boot project name Fix sparse warnings in zynqmp-clk, zynqmp handoff, board cmd: - Cover incorrect 0 length entries Versal NET: - Add bootmode logic - Support SPP production version - Add loadpdi command ZynqMP: - Clear pmufw node command ID handling - Change power domain behavior around zynqmp_pmufw_node() - Fix zynqmp cmd return values and pmufw command - Fix R5 tcm init and modes mmc: - Sync Versal NET emmc DT binding pcie: - Add support for ZynqMP PCIe root port video: - Add support for ZynqMP DP tools: - Fix debug message in relocate-rela

Merge tag v2023.07-rc4 into next

2023-06-12T18:55:33Z

Signed-off-by: Tom Rini

global: Use proper project name U-Boot

2023-06-12T11:24:31Z

Use proper project name in comments, Kconfig, readmes. Reviewed-by: Neil Armstrong Acked-by: Ilias Apalodimas Reviewed-by: Stefan Roese Reviewed-by: Qu Wenruo Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/0dbdf0432405c1c38ffca55703b6737a48219e79.1684307818.git.michal.simek@amd.com

mtd: spi: renesas: Add 4 bytes address mode support

2023-06-10T09:50:45Z

This patch adds 4-byte address mode support. Because traditional access based on FIFO/shift register, it's complex to specify information like opcode, address length, dummy bytes etc to flash. Replace the traditional access by spi-mem layer which is essential to make 4-byte address mode support possible. Reviewed-by: Marek Vasut Signed-off-by: Cong Dang Signed-off-by: Hai Pham Signed-off-by: Marek Vasut

mtd: spi: renesas: Add R-Car Gen4 support

2023-06-10T09:50:45Z

Support RPC SPI on R-Car Gen4 R8A779F0 S4 and R8A779G0 V4H SoCs. Reviewed-by: Marek Vasut Signed-off-by: Hai Pham Signed-off-by: Marek Vasut [Marek: Squash S4 and V4H patches, fix brackets around STRTIM2]

mtd: spi: renesas: Enable SPI_FLASH_SFDP_SUPPORT

2023-06-10T09:50:45Z

Enable support for parsing and auto discovery of parameters for SPI NOR flashes using Serial Flash Discoverable Parameters (SFDP) tables as per JESD216 standard. Reviewed-by: Marek Vasut Signed-off-by: Hai Pham Signed-off-by: Cong Dang Signed-off-by: Marek Vasut # Make SFDP the default unconditionally

mtd: spi: renesas: Extract strobe delay setting code into separate function

2023-06-10T09:50:45Z

Move strobe delay setting code into extra function and reflect the latest setting in datasheet (R-Car Gen3 v2.20, R-Car V3U v0.50). i.e. STRTIM[2:0] should be set to 110 (RCar M3-W) or 111 (Other products) This is also a preparation for new R-Car Gen4 SoC which has 4-bits STRTIM Reviewed-by: Marek Vasut Signed-off-by: Hai Pham Signed-off-by: Marek Vasut # Fix for RZ/A1

spi: rockchip_sfc: Use linux rockchip,sfc-no-dma prop

2023-05-18T00:44:04Z

Use the same prop as linux to control the use of fifo or dma mode. Also add a u-boot,spl-sfc-no-dma prop to control the same in SPL. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang

Revert "spi: zynq_qspi: Use dummy buswidth in dummy byte calculation"

2023-05-15T07:33:57Z

This reverts commit e09784728689de7949d4cdd559a9590e0bfcc702. The commit wrongly divides the dummy bytes by dummy bus width to calculate the dummy bytes. The framework already converts the dummy cycles to the number of bytes and the controller use the SPI flash command to determine the dummy cycles via the address width. Signed-off-by: Stefan Herbrechtsmeier Acked-by: Ashok Reddy Soma Link: https://lore.kernel.org/r/20230427065355.7413-1-stefan.herbrechtsmeier-oss@weidmueller.com Signed-off-by: Michal Simek