u-boot.git/drivers/spi, branch v2023.10

spi: mtk_spim: clear IRQ enable bits

2023-08-03T13:40:49Z

In u-boot we don't use IRQ. Instead, we poll busy bit in SPI_STATUS. However these IRQ enable bits may be set in previous boot stage (BootROM). If we leave these bits not cleared, although u-boot has disabled IRQ and nothing will happen, the linux kernel may encounter panic during initializing the spim driver due to IRQ event happens before IRQ handler is properly setup. This patch clear IRQ bits to prevent this from happening. Signed-off-by: SkyLake.Huang Signed-off-by: Weijie Gao Reviewed-by: Jagan Teki

spi: mtk_spim: get spi clk rate only once

2023-08-03T13:40:49Z

We don't really need to switch clk rate during operating SPIM controller. Get clk rate only once at driver probing. Signed-off-by: SkyLake.Huang Signed-off-by: Weijie Gao Reviewed-by: Jagan Teki

cadence_qspi: Enable flash reset for Versal NET platform

2023-07-21T07:00:38Z

Enable flash reset functionality for Versal NET platform. In cadence_qspi.c there is weak function defined for reset, hence remove the check for config, so that it will work for Versal and Versal NET platforms. Add register defines in Versal NET hardware.h for mini U-Boot flash reset. Add read_delay initialization for Versal NET also. Signed-off-by: Ashok Reddy Soma Link: https://lore.kernel.org/r/20230614120452.21019-1-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek

spi: zynq_qspi: Add missing prototype for zynq_qspi_mem_exec_op

2023-07-21T07:00:38Z

Add missing prototype to fix the sparse warning, warning: no previous prototype for 'zynq_qspi_mem_exec_op' [-Wmissing-prototypes]. Signed-off-by: Algapally Santosh Sagar Signed-off-by: Ashok Reddy Soma Link: https://lore.kernel.org/r/20230614090359.10809-4-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek

spi: xilinx_spi: Add missing prototype for xilinx_qspi_mem_exec_op

2023-07-21T07:00:38Z

Add missing prototype to fix the below sparse warning warning: no previous prototype for 'xilinx_qspi_mem_exec_op' [-Wmissing-prototypes] Signed-off-by: Algapally Santosh Sagar Signed-off-by: Ashok Reddy Soma Link: https://lore.kernel.org/r/20230614090359.10809-2-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek

spi: npcm_pspi: use ACTIVE_LOW flag for cs gpio and set default max_hz

2023-07-13T08:46:59Z

If cs gpio is requested with ACTIVE_HIGH flag, it will be pulled low(i.e. active). This is not what we expected. Signed-off-by: Jim Liu Reviewed-by: Jagan Teki

spi: soft_spi: Support the recommended soft spi properties

2023-07-13T08:29:57Z

According to Documentation/devicetree/bindings/spi/spi-gpio.yaml from Linux, the recommended spio-gpio properties are: sck-gpios, miso-gpios and mosi-gpios. gpio-sck, gpio-mosi and gpio-miso are considered deprecated. Currently, U-Boot only supports the deprecated properties. Allow the soft_spi driver to support both the new and old properties. Signed-off-by: Fabio Estevam Reviewed-by: Jagan Teki

spi: synquacer: remove SPI_TX_BYTE handling

2023-07-13T08:29:57Z

Current code expects that SPI_TX_BYTE is single bit mode but it is wrong. It indicates byte program mode, not single bit mode. If SPI_TX_DUAL, SPI_TX_QUAD and SPI_TX_OCTAL bits are not set, the default transfer bus width is single bit. Signed-off-by: Masahisa Kojima Reviewed-by: Ilias Apalodimas Reviewed-by: Jagan Teki

spi: bcmbca-hsspi: Add driver for newer HSSPI controller

2023-07-13T08:29:57Z

The newer BCMBCA SoCs such as BCM6756, BCM4912 and BCM6855 include an updated SPI controller that add the capability to allow the driver to control chip select explicitly. Driver can control and keep cs low between the transfers natively. Hence the dummy cs workaround or prepend mode found in the bcm63xx-hsspi driver are no longer needed and this new driver is much cleaner. Port from linux patch: Link: https://lore.kernel.org/r/20230209200246.141520-15-william.zhang@broadcom.com Signed-off-by: William Zhang Reviewed-by: Jagan Teki

spi: bcm63xx-hsspi: Add prepend mode support

2023-07-13T08:29:57Z

Due to the controller limitation to keep the chip select low during the bus idle time between the transfer, a dummy cs workaround was used when this driver was first upstreamed to the u-boot based on linux kernel driver. It basically picks the dummy cs as !actual_cs so typically dummy cs is 1 when most of the case only cs 0 is used in the board design. Then invert the polarity of both cs and tell the controller to start the transfers using dummy cs. Assuming both cs are active low before the inversion, effectively this keeps dummy cs high and actual cs low during the transfer and workaround the issue. This workaround requires that dummy cs 1 pin to is set to SPI chip selection function in the pinmux when the transfer clock is above 25MHz. The old chips likely have default pinmux set to chip select on the dummy cs pin so it works but this is not case for the new Broadband BCA chips and this workaround stop working. This is specifically an issue to support SPI NAND and SPI NOR flash because these flash devices can typically run at or above 100MHz. This patch utilizes the prepend feature of the controller to combine the multiple transfers in the same message to a single transfer when possible. This way there is no need to keep clock low between transfers and solve the issue without any pinmux requirement. Multiple transfers within a SPI message may be combined into one transfer if the following are all true: * One or more half duplex write transfer in single bit mode * Optional full duplex read/write at the end * No delay and cs_change between transfers Most of the SPI device meets this requirements such as SPI NOR, SPI NAND flash, Broadcom SPI voice card and etc. So this change switches to the prepend mode as the default mode. For any SPI message that does not meet the above requirement, we switch to original dummy cs mode but limit the clock rate to the safe 25MHz. Port from linux patch: Link: https://lore.kernel.org/r/20230209200246.141520-12-william.zhang@broadcom.com Signed-off-by: William Zhang Acked-by: Jagan Teki