<feed xmlns='http://www.w3.org/2005/Atom'>
<title>u-boot.git/drivers/spi, branch v2024.10</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/spi?h=v2024.10</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/drivers/spi?h=v2024.10'/>
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<updated>2024-09-08T23:10:33Z</updated>
<entry>
<title>mtd: spi: renesas: Add R-Car Gen4 DT compatible</title>
<updated>2024-09-08T23:10:33Z</updated>
<author>
<name>Marek Vasut</name>
<email>marek.vasut+renesas@mailbox.org</email>
</author>
<published>2024-08-31T20:31:48Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=2e255d2e6e1a8b56f594de4e6f969c97ce1aff46'/>
<id>urn:sha1:2e255d2e6e1a8b56f594de4e6f969c97ce1aff46</id>
<content type='text'>
Add device tree compatible string "renesas,rcar-gen4-rpc-if" to
the driver to match on upstream RPC DT node in R-Car Gen4 DTs.

Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@mailbox.org&gt;
</content>
</entry>
<entry>
<title>mtd: spi: renesas: Configure RPC PHY timing registers</title>
<updated>2024-09-08T23:10:33Z</updated>
<author>
<name>Marek Vasut</name>
<email>marek.vasut+renesas@mailbox.org</email>
</author>
<published>2024-08-31T20:31:47Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=d5162463243da66b27ac7ea96fcffb5da4c9a639'/>
<id>urn:sha1:d5162463243da66b27ac7ea96fcffb5da4c9a639</id>
<content type='text'>
Make sure RPC PHY timing registers are configured before performing
bus access. These registers might have been left unconfigured or may
have been configured by a prior stage bootloader and leaving them
unconfigured or misconfigured would interfere with U-Boot operation.

Set PHYOFFSET1 DDRTMG field to 3 which enables DDR timing adjustment
when SPIDRE or DRDRE = 0 and set PHYOFFSET2 OCTTMG field to 4 which
makes the interface operate in Serial flash or HyperFlash mode.

Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@mailbox.org&gt;
</content>
</entry>
<entry>
<title>mtd: spi: renesas: Configure DRDRENR register</title>
<updated>2024-09-08T23:10:33Z</updated>
<author>
<name>Marek Vasut</name>
<email>marek.vasut+renesas@mailbox.org</email>
</author>
<published>2024-08-31T20:31:46Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=c90795076b30c33a95bcaf6d89979543d31fdde1'/>
<id>urn:sha1:c90795076b30c33a95bcaf6d89979543d31fdde1</id>
<content type='text'>
Make sure DRDRENR register is configured before performing external
address space read. This register might have been configured by a
prior stage bootloader and leaving it unconfigured would interfere
with U-Boot operation. Since U-Boot RPC SPI driver does not support
DDR data transfer mode yet, set this register unconditionally to 0.

Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@mailbox.org&gt;
</content>
</entry>
<entry>
<title>mtd: spi: renesas: Write DRDMCR register once</title>
<updated>2024-09-08T23:10:33Z</updated>
<author>
<name>Marek Vasut</name>
<email>marek.vasut+renesas@mailbox.org</email>
</author>
<published>2024-08-31T20:31:45Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=3fba388e611e27e663c7cb4c1d1483e8909bdbc0'/>
<id>urn:sha1:3fba388e611e27e663c7cb4c1d1483e8909bdbc0</id>
<content type='text'>
Instead of writing DRDMCR with 0 first and then overwriting DRDMCR again
in case any dummy bytes have to be sent out, write DRDMCR in every case
with the amount of dummy bytes that have to be sent out. In case no dummy
bytes have to be sent out, the value written into DRDMCR is zero, so no
dummy bytes are sent out. No functional change.

Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@mailbox.org&gt;
</content>
</entry>
<entry>
<title>mtd: spi: renesas: Write DREAR register once</title>
<updated>2024-09-08T23:10:33Z</updated>
<author>
<name>Marek Vasut</name>
<email>marek.vasut+renesas@mailbox.org</email>
</author>
<published>2024-08-31T20:31:44Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=1cc7c7e119a31c64cf64d887374c95b58ffe9993'/>
<id>urn:sha1:1cc7c7e119a31c64cf64d887374c95b58ffe9993</id>
<content type='text'>
Instead of writing DREAR with 0 first and then overwriting DREAR again
in case of 4 byte addressing mode, write DREAR in every case once with
the correct content right away. No functional change.

Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@mailbox.org&gt;
</content>
</entry>
<entry>
<title>spi: sunxi: fix clock divider calculation for max frequency setting</title>
<updated>2024-08-06T10:20:10Z</updated>
<author>
<name>Michael Walle</name>
<email>mwalle@kernel.org</email>
</author>
<published>2024-07-18T20:42:53Z</published>
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<id>urn:sha1:541a1649e74787682902d820d0b79e16bad69a4f</id>
<content type='text'>
If the maximum frequency is requested, we still fall into the CDR2
handling. But there the minimal divider is 2. For the sun6i and sun8i we
can do better with the CDR1 setting where the minimal divider is 1:
  SPI_CLK = MOD_CLK / 2 ^ cdr with cdr = 0

Thus, handle the div = 1 case specially.

While at it, correct the comment above the calculation.

Signed-off-by: Michael Walle &lt;mwalle@kernel.org&gt;
Reviewed-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
</content>
</entry>
<entry>
<title>spi: sunxi: fix CDR2 calculation</title>
<updated>2024-08-06T10:20:10Z</updated>
<author>
<name>Michael Walle</name>
<email>mwalle@kernel.org</email>
</author>
<published>2024-07-18T20:42:52Z</published>
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<id>urn:sha1:6aadcb814d1e2203b0b953dda8d5fbdc7b3a9bf0</id>
<content type='text'>
The CDR2 divider calculation always yield a frequency greater than the
requested one. Use DIV_ROUND_UP() to keep the frequency equal or below
the requested one. This way, we can also drop the "if div &gt; 0" check
because we know for a fact that div cannot be zero.

FWIW, this aligns the CDR2 calculation with the linux driver.

Suggested-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
Signed-off-by: Michael Walle &lt;mwalle@kernel.org&gt;
Reviewed-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
</content>
</entry>
<entry>
<title>drivers: spi: Remove duplicate newlines</title>
<updated>2024-07-22T16:53:06Z</updated>
<author>
<name>Marek Vasut</name>
<email>marek.vasut+renesas@mailbox.org</email>
</author>
<published>2024-07-20T12:40:58Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=2159d507b04d7cf250009e7bff456f47b5342f11'/>
<id>urn:sha1:2159d507b04d7cf250009e7bff456f47b5342f11</id>
<content type='text'>
Drop all duplicate newlines. No functional change.

Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@mailbox.org&gt;
Reviewed-by: Michal Simek &lt;michal.simek@amd.com&gt;
</content>
</entry>
<entry>
<title>spi: sunxi: drop max_hz handling</title>
<updated>2024-07-16T00:40:40Z</updated>
<author>
<name>Michael Walle</name>
<email>mwalle@kernel.org</email>
</author>
<published>2024-07-12T17:14:56Z</published>
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<id>urn:sha1:674e4f994f5da537cab62ad86bc8bdf5acaae88c</id>
<content type='text'>
The driver is trying to read the "spi-max-frequency" property of the
*controller* driver node. There is no such property. The
"spi-max-frequency" property belongs to the SPI devices on the bus.

Right now, the driver will always fall back to the default value of 1MHz
and thus flash reads are very slow with just about 215kb/s.

In fact, the SPI uclass will already take care of everything and we just
have to clamp the frequency to the values the driver/hardware supports.
Thus, drop the whole max_hz handling.

Signed-off-by: Michael Walle &lt;mwalle@kernel.org&gt;
Reviewed-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
Tested-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
</content>
</entry>
<entry>
<title>spi: mtk_spim: add support for upstream mediatek, spi-ipm compatible</title>
<updated>2024-07-08T17:45:50Z</updated>
<author>
<name>Christian Marangi</name>
<email>ansuelsmth@gmail.com</email>
</author>
<published>2024-06-24T21:03:29Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=6f0e7663ef757f555f9d1f8bf17d606653881296'/>
<id>urn:sha1:6f0e7663ef757f555f9d1f8bf17d606653881296</id>
<content type='text'>
Upstream kernel linux use a different compatible mediatek,spi-ipm.

Add support for this compatible and add handling for the additional
clock similar to how it's done by the upstream driver and handling for
all the property enabled by default.

Signed-off-by: Christian Marangi &lt;ansuelsmth@gmail.com&gt;
</content>
</entry>
</feed>
