u-boot.git/drivers/spi, branch v2025.07

spi: fspi: dev_dbg() call assumes fdt_addr_t always a long long

2025-05-12T21:42:53Z

On 32-bit systems, e.g. i.mxrt-1170 fdt_addr_t may only be 32-bit. Cast to a "long long" for garbage avoidance. Signed-off-by: Jonathan Currier

spi: fspi: Add imxrt1170 device data

2025-05-12T21:42:53Z

Add the device specific driver data, and the clock configuration. Signed-off-by: Jonathan Currier

spi: fspi: involve lut_num for struct nxp_fspi_devtype_data

2025-05-12T21:42:53Z

The flexspi on different SoCs may have different number of LUTs. So involve lut_num in nxp_fspi_devtype_data to make distinguish. This patch prepare for the adding of imx8ulp. Fixes: ef89fd56bdfc ("arm64: dts: imx8ulp: add flexspi node") Cc: stable@kernel.org Signed-off-by: Haibo Chen Reviewed-by: Frank Li Link: https://patch.msgid.link/20240905094338.1986871-3-haibo.chen@nxp.com Signed-off-by: Mark Brown (Picked from linux 190b7e2efb1ed8435fc7431d9c7a2447d05d5066) Signed-off-by: Jonathan Currier

drivers: spi: Fix data loss issue in QSPI

2025-04-29T21:28:54Z

QSPI driver performs chip select operation before every read/write access. During this operation, driver needs to enable and disable the QSPI controller. This may cause data loss if there is inadvertent halting of any ongoing read/write operation. To avoid this scenario, waiting for the QSPI status to be idle before next read/write operation is implemented. Signed-off-by: Naresh Kumar Ravulapalli Reviewed-by: Tien Fong Chee

spi: fsl_qspi: Move AHB read buffer config after LUT

2025-04-25T11:52:59Z

When using CONFIG_FSL_QSPI_AHB_FULL_MAP the fsl_qspi_default_setup() sets the BFGENCR register to use the LUT(SEQID_LUT_AHB) before the Look Up Table is populated. This result in a situation that after 'sf probe' command any memory read from qspi using AHB will result in undefined behaviour (hang) untill first 'sf read' op is executed. Move the BFGENCR write to fsl_qspi_prepare_lut() to ensure that the setup is consistent. AHB reads will use the default LUT(index 0) setup by previous boot stage untill the first read op. Signed-off-by: Pawel Kochanowski

spi: cadence-qspi: Add disable STIG mode quikrs.

2025-04-24T14:25:43Z

Adding quirk to disable STIG mode since cadence controller has issue for read/write using the STIG mode. STIG mode is enabled by default since 2023.04 for small read/write(<8bytes). Updated STIG mode reading from dev_get_driver_data by assigning to platdata struct before read quirks variable. The STIG mode is disabled for normal read case and enabled for QSPI Jedec ID read/write since it requires STIG read/write. Porting from linux implementation https://lore.kernel.org/all/20241204063338.296959-1-niravkumar .l.rabara@intel.com/T/ Signed-off-by: Boon Khai Ng Reviewed-by: Tien Fong Chee

Merge tag 'xilinx-for-v2025.07-rc1' of https://source.denx.de/u-boot/custodians/u-boot-microblaze

2025-04-17T13:52:02Z

AMD/Xilinx/FPGA changes for v2025.07-rc1 AMD/Xilinx: - Synchronize enums around tcm_mode - Access bootmode registers via firmware interface - Setup default values for DEBUG_UART - Fix dfu alt buffer clearing - Convert loadpdi command to fpga - Fix board detection code - Minor defconfig updates Versal: - Wire multi_boot register Versal Gen 2: - Enable missing drivers - Wire i2c FRU decoding at start - Wire saving variables to different locations - Disable default DEBUG_UART - Wire USB/UFS boot and fix access via firmware interface - Minor fixes ZynqMP/Kria: - Enable mkfwumdata - Topic board update - Enhance binman configurations - Kria usb update BuR: - Add multiple Zynq based boards cadence_ospi: - Enable device reset fpga: - Add support for loading bitstream for Altera SoCs

spi: airoha: Add Airoha SPI NAND driver

2025-04-17T13:51:36Z

Add Airoha SPI NAND driver to permit usage of attached SNAND on the Airoha AN7581 SoC. While SPI controller supports DMA transation, due to U-Boot limitation we currently limit it to single command in Manual mode. Signed-off-by: Christian Marangi

spi: cadence_ospi: Add device reset via OSPI controller

2025-04-16T11:42:06Z

Add support for flash device reset via OSPI controller instead of using GPIO, as OSPI IP has device reset feature on Versal Gen2 platform. Also add compatible string for Versal Gen2 platform. Signed-off-by: Venkatesh Yadav Abbarapu Link: https://lore.kernel.org/r/20250311041317.2992862-1-venkatesh.abbarapu@amd.com Signed-off-by: Michal Simek

spi: tegra20_slink: fix CS polarity setup

2025-04-12T06:42:35Z

Add missing configuration of chip select polarity. Default polarity is LOW, which satisfies most cases but some devices require HIGH polarity and will not work. Signed-off-by: Svyatoslav Ryhel