u-boot.git/drivers/spi, branch v2025.10

spi: exynos: Remove extra term from test

2025-09-03T10:32:38Z

In spi_rx_tx there comes a test for execution of a code block that allows execution if rxp is not NULL or stopping is true. However all the code in this block relies on rxp being valid so allowing entry just if stopping is true does not make sense. So remove this from the test expression leaving just a NULL check for rxp. This issue was found by Smatch. Signed-off-by: Andrew Goodbody Signed-off-by: Minkyu Kang

spi: atmel_qspi: fix race condition in transfer completion check

2025-08-13T09:59:02Z

In atmel_qspi_transfer(), the status register is polled with: imr = QSPI_SR_INSTRE | QSPI_SR_CSR; return readl_poll_timeout(aq->regs + QSPI_SR, sr, (sr & imr) == imr, ATMEL_QSPI_TIMEOUT); However, this is racy: QSPI_SR_INSTRE can be set before QSPI_SR_CSR, and will then be cleared by the read. If that happens, the condition "(sr & imr) == imr" can never be true, and the function times out. This race condition is avoided in at91bootstrap by accumulating the status bits across reads until both bits have been observed: /* Poll INSTruction End and Chip Select Rise flags. */ imr = (QSPI_SR_INSTRE | QSPI_SR_CSR); sr = 0; do { udelay(1); sr |= qspi_readl(qspi, QSPI_SR) & imr; } while ((--timeout) && (sr != imr)); Update U-Boot's atmel_qspi_transfer() to use the same pattern, ensuring that both flags are observed even if they are not set simultaneously. Signed-off-by: Ramin Moussavi [eugen.hristev@linaro.org: remove 'sr' and fix commit msg] Signed-off-by: Eugen Hristev

spi: mvebu: Correct dependencies on MVEBU_A3700_SPI

2025-07-29T06:44:18Z

A dependency exposed by "make allyesconfig" is that the logic around this symbol was not quite correct. It needs to depend on ARCH_MVEBU and ARM64 and then select CLK_MVEBU. Signed-off-by: Tom Rini Reviewed-by: Stefan Roese

Revert "spi: cadence_qspi: Fix odd byte write issue in STIG mode"

2025-07-24T07:04:04Z

The buffer that is being used to write into the flash needs to be handled properly with padding of 0xFF. The place that this is done can be at a more generic place like spi-nor core. This reverts commit cd9123507003e07b13e61d72e14e493bb338e827. Signed-off-by: Prasanth Babu Mantena Reviewed-by: Neha Malcom Francis Reviewed-by: Venkatesh Yadav Abbarapu Link: https://lore.kernel.org/r/20250716070407.2082524-1-p-mantena@ti.com Signed-off-by: Michal Simek

spi: coreqspi: add xfer function for PolarFire SoC

2025-07-17T06:37:36Z

Add xfer function to PolarFire SoC coreqspi driver. The read and write operations are limited to one byte at a time instead of four as CMD18 (multiple block read) reads garbage when four byte ops are enabled. Signed-off-by: Eoin Dickson Acked-by: Leo Yu-Chi Liang

cadence_qspi: fix odd byte read issue in STIG mode

2025-07-08T13:01:25Z

In DDR mode, even bytes are read using DMA, while the remaining odd bytes are read using STIG mode. However, the data is not correctly transferred into the flash read data lower register because the supplementary byte of the STIG opcode is not being written to the opcode extension register, resulting in incorrect data being read. To resolve this issue, when using STIG transactions, the corresponding supplementary byte of any STIG opcode must be defined in the Opcode Extension Register (Lower). Issue has been observed on the Macronix MX66UM2G45G flashes. Signed-off-by: Prasad Kummari Signed-off-by: Venkatesh Yadav Abbarapu Link: https://lore.kernel.org/r/20250702053953.640046-1-venkatesh.abbarapu@amd.com Signed-off-by: Michal Simek

spi: cadence_qspi: Set tshsl_ns to at least one sclk_ns

2025-07-08T13:01:25Z

tshsl_ns is the clock delay for chip select deassert. This is the delay in master reference clocks for the length that the master mode chip select outputs are de-asserted between transactions. The minimum delay is always SCLK period to ensure the chip select is never re-asserted within one SCLK period. That is why tshsl_ns delay should be at least one sclk_ns value. If it is less than sclk_ns, set it equal to sclk_ns. Signed-off-by: Ashok Reddy Soma Signed-off-by: Venkatesh Yadav Abbarapu Link: https://lore.kernel.org/r/20250702065717.3871435-1-venkatesh.abbarapu@amd.com Signed-off-by: Michal Simek

spi: cadence_qspi: Fix odd byte write issue in STIG mode

2025-07-08T12:58:44Z

Starting from 'commit <8077d296adff> ("spi: cadence-quadspi: Use STIG mode for all ops with small payload") the utilization of STIG mode has been implemented for read and write operations involving less than 8 bytes of data. However, following this commit, encountering timeout issues occurs when writing odd bytes of data in DDR mode, as indicated below: "jedec_spi_nor flash@0: flash operation timed out SF: 3 bytes @ 0x0 Written: ERROR -110" To resolve this issue, the number of bytes to write has been updated specifically for DDR mode. Signed-off-by: Tejas Bhumkar Signed-off-by: Venkatesh Yadav Abbarapu Link: https://lore.kernel.org/r/20250704040444.671604-1-venkatesh.abbarapu@amd.com Signed-off-by: Michal Simek

nxp: Prepare macros for KVM changes

2025-06-27T17:48:20Z

A following patch is replacing our IO accessors with do { ... } while(0) ones in order to make them usable with KVM. That leads to an error eventually looking like this: arch/arm/include/asm/io.h:62:9: error: expected expression before 'do' 62 | do { \ | ^~ arch/arm/include/asm/io.h:211:41: note: in expansion of macro '__raw_writel' 211 | #define out_arch(type,endian,a,v) __raw_write##type(cpu_to_##endian(v),a) | ^~~~~~~~~~~ arch/arm/include/asm/io.h:223:25: note: in expansion of macro 'out_arch' 223 | #define out_be32(a,v) out_arch(l,be32,a,v) | ^~~~~~~~ drivers/spi/fsl_dspi.c:127:17: note: in expansion of macro 'out_be32' 127 | out_be32(addr, val) : out_le32(addr, val); | ^~~~~~~~ So adjust the current macros and code to be compatible with the upcoming change. Signed-off-by: Ilias Apalodimas Reviewed-by: Tom Rini

spi: fspi: dev_dbg() call assumes fdt_addr_t always a long long

2025-05-12T21:42:53Z

On 32-bit systems, e.g. i.mxrt-1170 fdt_addr_t may only be 32-bit. Cast to a "long long" for garbage avoidance. Signed-off-by: Jonathan Currier