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<title>u-boot.git/drivers/sysreset/Makefile, branch v2020.10</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>sysreset: Add Octeon sysreset driver</title>
<updated>2020-07-18T12:23:25+00:00</updated>
<author>
<name>Stefan Roese</name>
<email>sr@denx.de</email>
</author>
<published>2020-06-30T10:08:55+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=59aea37abf6bf6d5119a9e2f0237b26bf820b285'/>
<id>59aea37abf6bf6d5119a9e2f0237b26bf820b285</id>
<content type='text'>
This patch adds a UCLASS_SYSRESET sysreset driver for the Octeon SoC
family.

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
Reviewed-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
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<pre>
This patch adds a UCLASS_SYSRESET sysreset driver for the Octeon SoC
family.

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
Reviewed-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>sysreset: add reset controller based reboot driver</title>
<updated>2020-04-27T18:29:33+00:00</updated>
<author>
<name>Weijie Gao</name>
<email>weijie.gao@mediatek.com</email>
</author>
<published>2020-04-21T07:28:29+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=caf709229419b3ae6f6748d5c575a44a1bf30c14'/>
<id>caf709229419b3ae6f6748d5c575a44a1bf30c14</id>
<content type='text'>
Some chips provide their sysreset function in reset controller, which is
normally a bit written to 1 to perform the sysreset.

This patch adds a new sysreset driver to take advantage of it.

Reviewed-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Weijie Gao &lt;weijie.gao@mediatek.com&gt;
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<pre>
Some chips provide their sysreset function in reset controller, which is
normally a bit written to 1 to perform the sysreset.

This patch adds a new sysreset driver to take advantage of it.

Reviewed-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Weijie Gao &lt;weijie.gao@mediatek.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>sysreset_mpc83xx: fix mcp83xx -&gt; mpc83xx typo</title>
<updated>2019-12-13T18:01:53+00:00</updated>
<author>
<name>Rasmus Villemoes</name>
<email>rasmus.villemoes@prevas.dk</email>
</author>
<published>2019-12-13T15:47:58+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=875669da3bde6c76700eb74954d00d5df2fd337a'/>
<id>875669da3bde6c76700eb74954d00d5df2fd337a</id>
<content type='text'>
Signed-off-by: Rasmus Villemoes &lt;rasmus.villemoes@prevas.dk&gt;
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<pre>
Signed-off-by: Rasmus Villemoes &lt;rasmus.villemoes@prevas.dk&gt;
</pre>
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</content>
</entry>
<entry>
<title>x86: sysreset: Allow reset driver to be included in SPL/TPL</title>
<updated>2019-10-08T05:51:04+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2019-09-25T14:11:24+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=ff7abb85a43d501d29c43549eb3dceae25e00f10'/>
<id>ff7abb85a43d501d29c43549eb3dceae25e00f10</id>
<content type='text'>
At present this driver is always included in SPL and TPL, if U-Boot proper
enables it. Update the Makefile to provide full control using the existing
Kconfig options.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
[bmeng: make the Kconfig help text a little bit clearer]
Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
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<pre>
At present this driver is always included in SPL and TPL, if U-Boot proper
enables it. Update the Makefile to provide full control using the existing
Kconfig options.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
[bmeng: make the Kconfig help text a little bit clearer]
Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>sysreset: socfpga: stratix10: add sysreset driver</title>
<updated>2019-07-21T10:45:10+00:00</updated>
<author>
<name>Simon Goldschmidt</name>
<email>simon.k.r.goldschmidt@gmail.com</email>
</author>
<published>2019-07-15T19:47:54+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=690c12965f72129838adc1a2465b7a80d4bc2ed3'/>
<id>690c12965f72129838adc1a2465b7a80d4bc2ed3</id>
<content type='text'>
This adds a UCLASS_SYSRESET sysreset driver for socfgpa stratix10.

Signed-off-by: Simon Goldschmidt &lt;simon.k.r.goldschmidt@gmail.com&gt;
</content>
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<pre>
This adds a UCLASS_SYSRESET sysreset driver for socfgpa stratix10.

Signed-off-by: Simon Goldschmidt &lt;simon.k.r.goldschmidt@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>sysreset: socfpga: gen5: add sysreset driver</title>
<updated>2019-07-21T10:45:10+00:00</updated>
<author>
<name>Simon Goldschmidt</name>
<email>simon.k.r.goldschmidt@gmail.com</email>
</author>
<published>2019-07-15T19:47:53+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=1f1668883d0e1ec68a9b4658ec746ef21b3148da'/>
<id>1f1668883d0e1ec68a9b4658ec746ef21b3148da</id>
<content type='text'>
This adds a UCLASS_SYSRESET sysreset driver for socfgpa gen5.

Signed-off-by: Simon Goldschmidt &lt;simon.k.r.goldschmidt@gmail.com&gt;
</content>
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<pre>
This adds a UCLASS_SYSRESET sysreset driver for socfgpa gen5.

Signed-off-by: Simon Goldschmidt &lt;simon.k.r.goldschmidt@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>sysreset: enable driver support in SPL/TPL</title>
<updated>2019-05-08T09:34:12+00:00</updated>
<author>
<name>Kever Yang</name>
<email>kever.yang@rock-chips.com</email>
</author>
<published>2019-04-02T12:41:25+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=09259fce1e8b4ac34a47d4590f42878a38b42826'/>
<id>09259fce1e8b4ac34a47d4590f42878a38b42826</id>
<content type='text'>
SPL/TPL also need use sysreset for some feature like panic callback.

Signed-off-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</content>
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<pre>
SPL/TPL also need use sysreset for some feature like panic callback.

Signed-off-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>mpc83xx: Add sysreset driver</title>
<updated>2018-09-18T06:01:18+00:00</updated>
<author>
<name>Mario Six</name>
<email>mario.six@gdsys.cc</email>
</author>
<published>2018-08-06T08:23:35+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=76fdad1f214beb5170f9979761286279fe8a234a'/>
<id>76fdad1f214beb5170f9979761286279fe8a234a</id>
<content type='text'>
Add a sysreset driver for the MPC83xx platform.

Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Mario Six &lt;mario.six@gdsys.cc&gt;
</content>
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<pre>
Add a sysreset driver for the MPC83xx platform.

Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Mario Six &lt;mario.six@gdsys.cc&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>sysreset: Add TI System Control Interface (TI SCI) sysreset driver</title>
<updated>2018-09-11T12:32:55+00:00</updated>
<author>
<name>Andreas Dannenberg</name>
<email>dannenberg@ti.com</email>
</author>
<published>2018-08-27T10:27:46+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=694b05240161eecc9628d5816fbf3d37f3c32e2d'/>
<id>694b05240161eecc9628d5816fbf3d37f3c32e2d</id>
<content type='text'>
Devices from the TI K3 family of SoCs like the AM654x contain a Device
Management and Security Controller (SYSFW) that manages the low-level
device control (like clocks, resets etc) for the various hardware
modules present on the SoC. These device control operations are provided
to the host processor OS through a communication protocol called the TI
System Control Interface (TI SCI) protocol.

This patch adds a system reset driver that communicates to the system
controller over the TI SCI protocol for allowing to perform a system-
wide SoC reset.

Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
Signed-off-by: Andreas Dannenberg &lt;dannenberg@ti.com&gt;
Signed-off-by: Lokesh Vutla &lt;lokeshvutla@ti.com&gt;
</content>
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<pre>
Devices from the TI K3 family of SoCs like the AM654x contain a Device
Management and Security Controller (SYSFW) that manages the low-level
device control (like clocks, resets etc) for the various hardware
modules present on the SoC. These device control operations are provided
to the host processor OS through a communication protocol called the TI
System Control Interface (TI SCI) protocol.

This patch adds a system reset driver that communicates to the system
controller over the TI SCI protocol for allowing to perform a system-
wide SoC reset.

Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
Signed-off-by: Andreas Dannenberg &lt;dannenberg@ti.com&gt;
Signed-off-by: Lokesh Vutla &lt;lokeshvutla@ti.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>dm: sysreset: x86: Add a sysreset driver</title>
<updated>2018-07-20T01:33:22+00:00</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2018-07-03T09:48:40+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=fabb2b4c7f28e672080a97980c4bb1a45375cbb3'/>
<id>fabb2b4c7f28e672080a97980c4bb1a45375cbb3</id>
<content type='text'>
This adds a generic reset driver for x86 processor.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
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<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This adds a generic reset driver for x86 processor.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
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