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<title>u-boot.git/drivers/sysreset/sysreset_resetctl.c, branch v2021.01</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>sysreset: add reset controller based reboot driver</title>
<updated>2020-04-27T18:29:33+00:00</updated>
<author>
<name>Weijie Gao</name>
<email>weijie.gao@mediatek.com</email>
</author>
<published>2020-04-21T07:28:29+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=caf709229419b3ae6f6748d5c575a44a1bf30c14'/>
<id>caf709229419b3ae6f6748d5c575a44a1bf30c14</id>
<content type='text'>
Some chips provide their sysreset function in reset controller, which is
normally a bit written to 1 to perform the sysreset.

This patch adds a new sysreset driver to take advantage of it.

Reviewed-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Weijie Gao &lt;weijie.gao@mediatek.com&gt;
</content>
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<pre>
Some chips provide their sysreset function in reset controller, which is
normally a bit written to 1 to perform the sysreset.

This patch adds a new sysreset driver to take advantage of it.

Reviewed-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Weijie Gao &lt;weijie.gao@mediatek.com&gt;
</pre>
</div>
</content>
</entry>
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