u-boot.git/drivers/sysreset, branch v2026.01 Unnamed repository; edit this file 'description' to name the repository. sysreset: Tighten some sysreset driver dependencies 2025-08-14T16:59:35+00:00 Tom Rini trini@konsulko.com 2025-08-04T21:57:19+00:00 38931172edd71c27101ac19361819d945ae337d8 The MPC83xx sysreset driver cannot build without access to some architecture specific header files. Express that requirements in Kconfig as well. Reviewed-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com> 
The MPC83xx sysreset driver cannot build without access to some
architecture specific header files. Express that requirements in Kconfig
as well.

Reviewed-by: Peter Robinson <pbrobinson@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
sysreset: socfpga: soc64: Enable L2 reset 2025-08-08T14:20:50+00:00 Alif Zakuan Yuslaimi alif.zakuan.yuslaimi@altera.com 2025-08-04T01:24:44+00:00 c8f5166cff0ccdb1966ed786dba88e9548ce632e Put all slave CPUs (CPU1-3) into WFI mode. Master CPU (CPU0) writes the magic word into system manager's scratch register to indicate the system has performed L2 reset and request reset manager to perform hardware handshake and then trigger L2 reset. CPU0 put itself into WFI mode. L2 reset will reboot all HPS CPU cores after which all HPS cores are in WFI mode. L2 reset is followed by warm reset request by SPL via RMR_EL3 system register. Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com> 
Put all slave CPUs (CPU1-3) into WFI mode. Master CPU (CPU0) writes
the magic word into system manager's scratch register to indicate
the system has performed L2 reset and request reset manager to
perform hardware handshake and then trigger L2 reset. CPU0 put
itself into WFI mode. L2 reset will reboot all HPS CPU cores after
which all HPS cores are in WFI mode. L2 reset is followed by warm
reset request by SPL via RMR_EL3 system register.

Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
sysreset: psci: Fix SPL dependency 2025-07-23T23:37:11+00:00 Michal Simek michal.simek@amd.com 2025-07-17T08:41:32+00:00 cf13f33d3a684c12f1ef835793cd66193df00c47 SYSRESET_PSCI should select SPL_ARM_PSCI_FW only when SPL_SYSRESET is enabled/required. This change saves 1.6kB on Xilinx ZynqMP Kria platform. Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Tom Rini <trini@konsulko.com> 
SYSRESET_PSCI should select SPL_ARM_PSCI_FW only when SPL_SYSRESET is
enabled/required. This change saves 1.6kB on Xilinx ZynqMP Kria platform.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
sysreset: implement MAX9807 sysreset functions 2025-05-08T05:30:53+00:00 Svyatoslav Ryhel clamor95@gmail.com 2024-10-06T13:51:21+00:00 5f3588a94d219818c1b3a2dac4d063f77f48a5ef MAX8907 PMIC has embedded poweroff function used by some device to initiane device power off. Implement it as optional sysreset driver guarded by kconfig option and system-power-controller device tree property. Tested-by: Ion Agorria <ion@agorria.com> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> 
MAX8907 PMIC has embedded poweroff function used by some device to initiane
device power off. Implement it as optional sysreset driver guarded by
kconfig option and system-power-controller device tree property.

Tested-by: Ion Agorria <ion@agorria.com>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
sysreset: diverge GPIO reset and poweroff configs per-phase 2025-04-12T06:42:36+00:00 Svyatoslav Ryhel clamor95@gmail.com 2025-03-29T11:02:03+00:00 782bd104b696d9a10999f285a68d87e4fc85acb6 GPIO reset and power-off functionality depends on device tree data, which is often absent in SPL or TPL. To address this, incorporate PHASE_ into the config option and add Kconfig option or each phase. Adjust SYSRESET_GPIO and POWEROFF_GPIO uses to address possible regressions. Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> 
GPIO reset and power-off functionality depends on device tree data, which
is often absent in SPL or TPL. To address this, incorporate PHASE_ into the
config option and add Kconfig option or each phase.

Adjust SYSRESET_GPIO and POWEROFF_GPIO uses to address possible
regressions.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
sysreset: qcom-pshold: remove ARCH_IPQ40XX dependency 2025-03-17T13:38:19+00:00 Sam Day me@samcday.com 2025-01-25T19:59:20+00:00 11c7187253df306c04c1b48142ed046dc1351c45 Depending on ARCH_IPQ40XX is too restrictive, as this architecture is explicitly armv7. This driver is also used on msm8916 devices, which have cortex-a53 armv8 cores. Signed-off-by: Sam Day <me@samcday.com> Link: https://lore.kernel.org/r/20250125-msm8916-sysreset-v1-2-62073932ff0e@samcday.com Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> 
Depending on ARCH_IPQ40XX is too restrictive, as this architecture is
explicitly armv7. This driver is also used on msm8916 devices, which
have cortex-a53 armv8 cores.

Signed-off-by: Sam Day <me@samcday.com>
Link: https://lore.kernel.org/r/20250125-msm8916-sysreset-v1-2-62073932ff0e@samcday.com
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
global: Rename SPL_TPL_ to PHASE_ 2024-10-11T17:44:48+00:00 Simon Glass sjg@chromium.org 2024-09-30T01:49:54+00:00 5c10c8badf8233cac1593cd2bef4d0379ac9e5bd Use PHASE_ as the symbol to select a particular XPL build. This means that SPL_TPL_ is no-longer set. Update the comment in bootstage to refer to this symbol, instead of SPL_ Signed-off-by: Simon Glass <sjg@chromium.org> 
Use PHASE_ as the symbol to select a particular XPL build. This means
that SPL_TPL_ is no-longer set.

Update the comment in bootstage to refer to this symbol, instead of
SPL_

Signed-off-by: Simon Glass <sjg@chromium.org>
drivers: Use CONFIG_XPL_BUILD instead of CONFIG_SPL_BUILD 2024-10-11T17:44:48+00:00 Simon Glass sjg@chromium.org 2024-09-30T01:49:48+00:00 371dc068bbf50c6ed6146c04ec83b644bcc79249 Use the new symbol to refer to any 'SPL' build, including TPL and VPL Signed-off-by: Simon Glass <sjg@chromium.org> 
Use the new symbol to refer to any 'SPL' build, including TPL and VPL

Signed-off-by: Simon Glass <sjg@chromium.org>
xpl: Rename spl_phase() to xpl_phase() 2024-10-11T17:44:47+00:00 Simon Glass sjg@chromium.org 2024-09-30T01:49:36+00:00 456bdb70def1fe371f964e82158a53f6baf1d3a4 Rename this function to indicate that it refers to any xPL phase. Signed-off-by: Simon Glass <sjg@chromium.org> 
Rename this function to indicate that it refers to any xPL phase.

Signed-off-by: Simon Glass <sjg@chromium.org>
drivers: sysreset: Remove duplicate newlines 2024-07-22T16:53:06+00:00 Marek Vasut marek.vasut+renesas@mailbox.org 2024-07-20T12:40:59+00:00 c77c054aa52517362f9c0c2650399c61a48f088d Drop all duplicate newlines. No functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> 
Drop all duplicate newlines. No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>