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<title>u-boot.git/drivers/timer/Kconfig, branch v2018.05</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>timer: stm32: Add timer support for STM32 SoCs family</title>
<updated>2018-03-14T01:45:37+00:00</updated>
<author>
<name>Patrice Chotard</name>
<email>patrice.chotard@st.com</email>
</author>
<published>2018-02-07T09:44:45+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=5120a083e797aec3180fbda9ab845486da990909'/>
<id>5120a083e797aec3180fbda9ab845486da990909</id>
<content type='text'>
This timer driver is using GPT Timer (General Purpose Timer)
available on all STM32 SOCs family.
This driver can be used on STM32F4/F7 and H7 SoCs family

Signed-off-by: Patrice Chotard &lt;patrice.chotard@st.com&gt;
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<pre>
This timer driver is using GPT Timer (General Purpose Timer)
available on all STM32 SOCs family.
This driver can be used on STM32F4/F7 and H7 SoCs family

Signed-off-by: Patrice Chotard &lt;patrice.chotard@st.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>atcpit100: timer: Remove arch dependency.</title>
<updated>2017-11-30T01:39:31+00:00</updated>
<author>
<name>Rick Chen</name>
<email>rick@andestech.com</email>
</author>
<published>2017-11-23T04:48:46+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=0f4a395f782a2801842492d5b365ed095a1e69ef'/>
<id>0f4a395f782a2801842492d5b365ed095a1e69ef</id>
<content type='text'>
ATCPIT100 is often used in AE3XX platform which is
based on NDS32 architecture recently. But in the future
Andestech will have AE250 platform which is embeded
ATCPIT100 timer based on RISCV architecture.

Signed-off-by: Rick Chen &lt;rick@andestech.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
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<pre>
ATCPIT100 is often used in AE3XX platform which is
based on NDS32 architecture recently. But in the future
Andestech will have AE250 platform which is embeded
ATCPIT100 timer based on RISCV architecture.

Signed-off-by: Rick Chen &lt;rick@andestech.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ae3xx: timer: Rename AE3XX to ATCPIT100</title>
<updated>2017-11-30T01:38:54+00:00</updated>
<author>
<name>Rick Chen</name>
<email>rickchen36@gmail.com</email>
</author>
<published>2017-11-28T01:23:23+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=fa3e354b2bcc9b07c89d0be190dd0e75cf54d6c6'/>
<id>fa3e354b2bcc9b07c89d0be190dd0e75cf54d6c6</id>
<content type='text'>
ATCPIT100 is Andestech timer IP which is embeded
in AE3XX and AE250 boards. So rename AE3XX to
ATCPIT100 will be more make sence.

Signed-off-by: rick &lt;rick@andestech.com&gt;
Signed-off-by: Rick Chen &lt;rickchen36@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
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<pre>
ATCPIT100 is Andestech timer IP which is embeded
in AE3XX and AE250 boards. So rename AE3XX to
ATCPIT100 will be more make sence.

Signed-off-by: rick &lt;rick@andestech.com&gt;
Signed-off-by: Rick Chen &lt;rickchen36@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>driver: timer: Add the Atmel PIT timer driver</title>
<updated>2017-08-26T18:56:08+00:00</updated>
<author>
<name>Wenyou.Yang@microchip.com</name>
<email>Wenyou.Yang@microchip.com</email>
</author>
<published>2017-08-15T09:40:26+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=47edaea4943c99f560f3d055b2468333e9192628'/>
<id>47edaea4943c99f560f3d055b2468333e9192628</id>
<content type='text'>
Add the new Atmel PIT timer driver, which supports the driver model
and device tree.

Signed-off-by: Wenyou Yang &lt;wenyou.yang@microchip.com&gt;
</content>
<content type='xhtml'>
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<pre>
Add the new Atmel PIT timer driver, which supports the driver model
and device tree.

Signed-off-by: Wenyou Yang &lt;wenyou.yang@microchip.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>rockchip: timer: add device-model timer driver for RK3368 (and similar)</title>
<updated>2017-08-13T15:12:36+00:00</updated>
<author>
<name>Philipp Tomsich</name>
<email>philipp.tomsich@theobroma-systems.com</email>
</author>
<published>2017-07-28T15:43:19+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=1168d2dd4b370155b499b995fde7da5a8782ead4'/>
<id>1168d2dd4b370155b499b995fde7da5a8782ead4</id>
<content type='text'>
This adds a device-model driver for the timer block in the RK3368 (and
similar devices that share the same timer block, such as the RK3288) for
the down-counting (i.e. non-secure) timers.

This allows us to configure U-Boot for the RK3368 in such a way that
we can run with the secure timer inaccessible or uninitialised (note
that the ARMv8 generic timer does not count, if the secure timer is
not enabled).

Signed-off-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
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<pre>
This adds a device-model driver for the timer block in the RK3368 (and
similar devices that share the same timer block, such as the RK3288) for
the down-counting (i.e. non-secure) timers.

This allows us to configure U-Boot for the RK3368 in such a way that
we can run with the secure timer inaccessible or uninitialised (note
that the ARMv8 generic timer does not count, if the secure timer is
not enabled).

Signed-off-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>dm: timer: normalise SPL and TPL support</title>
<updated>2017-08-13T15:12:36+00:00</updated>
<author>
<name>Philipp Tomsich</name>
<email>philipp.tomsich@theobroma-systems.com</email>
</author>
<published>2017-07-28T15:38:42+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=e9e5d9d29f747d7c14944129ce523d9d5efe9c0b'/>
<id>e9e5d9d29f747d7c14944129ce523d9d5efe9c0b</id>
<content type='text'>
To fully support DM timer in SPL and TPL, we need a few things cleaned
up and normalised:
- inclusion of the uclass and drivers should be an all-or-nothing
  decision for each stage and under control of $(SPL_TPL_)TIMER
  instead of having the two-level configuration with TIMER and
  $(SPL_TPL_)TIMER_SUPPORT
- when $(SPL_TPL_)TIMER is enabled, the ARMv8 generic timer code can
  not be compiled in

This normalises configuration to $(SPL_TPL_)TIMER and moves the config
options to drivers/timer/Kconfig (and cleans up the collateral damage
to some defconfigs that had SPL_TIMER_SUPPORT enabled).

Signed-off-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
<content type='xhtml'>
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<pre>
To fully support DM timer in SPL and TPL, we need a few things cleaned
up and normalised:
- inclusion of the uclass and drivers should be an all-or-nothing
  decision for each stage and under control of $(SPL_TPL_)TIMER
  instead of having the two-level configuration with TIMER and
  $(SPL_TPL_)TIMER_SUPPORT
- when $(SPL_TPL_)TIMER is enabled, the ARMv8 generic timer code can
  not be compiled in

This normalises configuration to $(SPL_TPL_)TIMER and moves the config
options to drivers/timer/Kconfig (and cleans up the collateral damage
to some defconfigs that had SPL_TIMER_SUPPORT enabled).

Signed-off-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>x86: kconfig: Select TIMER and X86_TSC_TIMER</title>
<updated>2017-08-01T12:17:02+00:00</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2017-07-30T13:23:07+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=0ce9c57620a375bf58ae8d9a20698fb295bd1584'/>
<id>0ce9c57620a375bf58ae8d9a20698fb295bd1584</id>
<content type='text'>
Without a timer, U-Boot just doesn't boot. This is not something
we can turn off.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Andy Shevchenko &lt;andy.shevchenko@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
<content type='xhtml'>
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<pre>
Without a timer, U-Boot just doesn't boot. This is not something
we can turn off.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Andy Shevchenko &lt;andy.shevchenko@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>nds32: Support AE3XX platform.</title>
<updated>2017-05-22T06:05:46+00:00</updated>
<author>
<name>rick</name>
<email>rick@andestech.com</email>
</author>
<published>2017-05-18T06:37:53+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=b841b6e94662b3b21a56d6ecaab64dcdfb0d311c'/>
<id>b841b6e94662b3b21a56d6ecaab64dcdfb0d311c</id>
<content type='text'>
Support Andestech AE3xx platform: serial, timer device tree flow.

Signed-off-by: rick &lt;rick@andestech.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Support Andestech AE3xx platform: serial, timer device tree flow.

Signed-off-by: rick &lt;rick@andestech.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>nds32: Support AG101P timer DM.</title>
<updated>2017-05-22T06:05:40+00:00</updated>
<author>
<name>rick</name>
<email>rick@andestech.com</email>
</author>
<published>2017-05-17T02:59:20+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=f5076f869855045e527de7f1367c65f55a2b1448'/>
<id>f5076f869855045e527de7f1367c65f55a2b1448</id>
<content type='text'>
Support AG101P timer device tree flow.

Signed-off-by: rick &lt;rick@andestech.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Support AG101P timer device tree flow.

Signed-off-by: rick &lt;rick@andestech.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>drivers: timer: Introduce ARC timer driver</title>
<updated>2017-03-24T11:20:55+00:00</updated>
<author>
<name>Vlad Zakharov</name>
<email>vzakhar@synopsys.com</email>
</author>
<published>2017-03-21T11:49:47+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=ad9b5f77dffaa38ea830af94cd5de3450318f97c'/>
<id>ad9b5f77dffaa38ea830af94cd5de3450318f97c</id>
<content type='text'>
This commit introduces timer driver for ARC.

ARC timers are configured via ARC AUX registers so we use special
functions to access timer control registers.

This driver allows utilization of either timer0 or timer1
depending on which one is available in real hardware. Essentially
only existing timers should be mentioned in board's Device Tree
description.

Signed-off-by: Vlad Zakharov &lt;vzakhar@synopsys.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
<content type='xhtml'>
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<pre>
This commit introduces timer driver for ARC.

ARC timers are configured via ARC AUX registers so we use special
functions to access timer control registers.

This driver allows utilization of either timer0 or timer1
depending on which one is available in real hardware. Essentially
only existing timers should be mentioned in board's Device Tree
description.

Signed-off-by: Vlad Zakharov &lt;vzakhar@synopsys.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
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