u-boot.git/drivers/timer/Makefile, branch v2022.07 Unnamed repository; edit this file 'description' to name the repository. timer: npcm: Add NPCM timer support 2022-05-05T13:28:47+00:00 Jim Liu jim.t90615@gmail.com 2022-04-19T05:32:22+00:00 b789e4f215614e3aee2f78925683dc722ca617fc Add Nuvoton BMC NPCM7xx/NPCM8xx timer driver. Signed-off-by: Jim Liu <JJLIU0@nuvoton.com> Signed-off-by: Stanley Chu <yschu@nuvoton.com> 
Add Nuvoton BMC NPCM7xx/NPCM8xx timer driver.

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
Signed-off-by: Stanley Chu <yschu@nuvoton.com>
timers: atmel_pit: introduce CONFIG_SPL_ATMEL_PIT_TIMER 2022-04-26T06:54:41+00:00 Eugen Hristev eugen.hristev@microchip.com 2022-04-04T08:35:51+00:00 632422d4b333f3580b9fd28c424ff728ed3d3bad This commit allows the ATMEL_PIT_TIMER driver to be unselected in SPL and be selected in u-boot proper. The SPL can use a different timer. By having a separate Kconfig for ATMEL_TCB in SPL, the size of the SPL decreases by 0.3 KBytes. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> 
This commit allows the ATMEL_PIT_TIMER driver to be unselected in SPL and be
selected in u-boot proper. The SPL can use a different timer.
By having a separate Kconfig for ATMEL_TCB in SPL, the size of the SPL
decreases by 0.3 KBytes.

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
timers: atmel_tcb: introduce CONFIG_SPL_ATMEL_TCB 2022-04-26T06:53:49+00:00 Eugen Hristev eugen.hristev@microchip.com 2022-04-04T08:35:50+00:00 e135d2c2f385fc1cefcea64cf775c6f0267945a2 This commit allows the ATMEL_TCB driver to be unselected in SPL and be selected in u-boot proper. The SPL can use a different timer. By having a separate Kconfig for ATMEL_TCB in SPL, the size of the SPL decreases by 1 KByte. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> 
This commit allows the ATMEL_TCB driver to be unselected in SPL and be
selected in u-boot proper. The SPL can use a different timer.
By having a separate Kconfig for ATMEL_TCB in SPL, the size of the SPL
decreases by 1 KByte.

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
nds32: Remove the architecture 2022-04-25T20:04:05+00:00 Tom Rini trini@konsulko.com 2022-04-06T13:21:25+00:00 11232139e399e70641410356ae6b278113d90f16 As removal of nds32 has been ack'd for the Linux kernel, remove support here as well. Cc: Rick Chen <rick@andestech.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com> 
As removal of nds32 has been ack'd for the Linux kernel, remove support
here as well.

Cc: Rick Chen <rick@andestech.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Rick Chen <rick@andestech.com>
timer: atmel_tcb_timer: add atmel_tcb driver 2022-04-01T12:42:46+00:00 Clément Léger clement.leger@bootlin.com 2022-03-31T08:55:06+00:00 70fb1ae9dd30b1dc6cf0c6ba585f822ef58106e5 Add a driver for the timer counter block that can be found on sama5d2. This driver will be used when booting under OP-TEE since the pit timer which is part of the SYSC is secured. Channel 1 & 2 are configured to be chained together which allows to have a 64bits counter. Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Clément Léger <clement.leger@bootlin.com> 
Add a driver for the timer counter block that can be found on sama5d2.
This driver will be used when booting under OP-TEE since the pit timer
which is part of the SYSC is secured. Channel 1 & 2 are configured to
be chained together which allows to have a 64bits counter.

Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>
timer: imx-gpt: Add timer support for i.MX SoCs family 2021-06-09T11:01:33+00:00 Giulio Benetti giulio.benetti@benettiengineering.com 2021-05-13T10:18:31+00:00 f8c8573b85765f60d4c4ef022a1fc57bbb2dd704 This timer driver uses GPT Timer (General Purpose Timer) available on a lot of i.MX SoCs family. This driver deals with both 24Mhz oscillator as well as peripheral clock. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> [Giulio: added the driver's stub and handled peripheral clock prescaler setting making driver to work correctly] Signed-off-by: Jesse Taube <mr.bossman075@gmail.com> [Jesse: added init, setting prescaler for 24Mhz support and enabling timer] 
This timer driver uses GPT Timer (General Purpose Timer) available on
a lot of i.MX SoCs family. This driver deals with both 24Mhz oscillator
as well as peripheral clock.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
[Giulio: added the driver's stub and handled peripheral clock prescaler
setting making driver to work correctly]
Signed-off-by: Jesse Taube <mr.bossman075@gmail.com>
[Jesse: added init, setting prescaler for 24Mhz support and enabling
timer]
riscv: Split SiFive CLINT support between SPL and U-Boot proper 2021-05-17T08:42:24+00:00 Bin Meng bmeng.cn@gmail.com 2021-05-11T12:04:12+00:00 a6d7e8c9149f5f1b94f68129fbe5dec9e1e1489d At present there is only one Kconfig option CONFIG_SIFIVE_CLINT to control the enabling of SiFive CLINT support in both SPL (M-mode) and U-Boot proper (S-mode). So for a typical SPL config that the SiFive CLINT driver is enabled in both SPL and U-Boot proper, that means the S-mode U-Boot tries to access the memory-mapped CLINT registers directly, instead of the normal 'rdtime' instruction. This was not a problem before, as the hardware does not forbid the access from S-mode. However this becomes an issue now with OpenSBI commit 8b569803475e ("lib: utils/sys: Add CLINT memregion in the root domain") that the SiFive CLINT register space is protected by PMP for M-mode access only. U-Boot proper does not boot any more with the latest OpenSBI, that access exceptions are fired forever from U-Boot when trying to read the timer value via the SiFive CLINT driver in U-Boot. To solve this, we need to split current SiFive CLINT support between SPL and U-Boot proper, using 2 separate Kconfig options. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> 
At present there is only one Kconfig option CONFIG_SIFIVE_CLINT to
control the enabling of SiFive CLINT support in both SPL (M-mode)
and U-Boot proper (S-mode). So for a typical SPL config that the
SiFive CLINT driver is enabled in both SPL and U-Boot proper, that
means the S-mode U-Boot tries to access the memory-mapped CLINT
registers directly, instead of the normal 'rdtime' instruction.

This was not a problem before, as the hardware does not forbid the
access from S-mode. However this becomes an issue now with OpenSBI
commit 8b569803475e ("lib: utils/sys: Add CLINT memregion in the root domain")
that the SiFive CLINT register space is protected by PMP for M-mode
access only. U-Boot proper does not boot any more with the latest
OpenSBI, that access exceptions are fired forever from U-Boot when
trying to read the timer value via the SiFive CLINT driver in U-Boot.

To solve this, we need to split current SiFive CLINT support between
SPL and U-Boot proper, using 2 separate Kconfig options.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
riscv: Move timer portions of SiFive CLINT to drivers/timer 2020-10-26T02:01:28+00:00 Sean Anderson seanga2@gmail.com 2020-10-26T01:46:58+00:00 47d7e3b5eb72fd540930c830d568ece19b3defa0 Half of this driver is a DM-based timer driver, and half is RISC-V-specific IPI code. Move the timer portions in with the other timer drivers. The KConfig is not moved, since it also enables IPIs. It could also be split into two configs, but no boards use the timer but not the IPI atm, so I haven't split it. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com> 
Half of this driver is a DM-based timer driver, and half is RISC-V-specific
IPI code. Move the timer portions in with the other timer drivers. The
KConfig is not moved, since it also enables IPIs. It could also be split
into two configs, but no boards use the timer but not the IPI atm, so I
haven't split it.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Rick Chen <rick@andestech.com>
timer: Add _TIMER suffix to Andes PLMT Kconfig 2020-10-26T02:01:28+00:00 Sean Anderson seanga2@gmail.com 2020-10-26T01:46:57+00:00 7dbebebb7949655f35d90c612eaf92e3d2c9ed24 This matches the naming scheme of other timer drivers. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com> 
This matches the naming scheme of other timer drivers.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Rick Chen <rick@andestech.com>
riscv: Move Andes PLMT driver to drivers/timer 2020-10-26T02:01:28+00:00 Sean Anderson seanga2@gmail.com 2020-10-26T01:46:56+00:00 79b135f1f937296fbe40ffa8500b531a7e1a0e9d This is a regular timer driver, and should live with the other timer drivers. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com> 
This is a regular timer driver, and should live with the other timer
drivers.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Rick Chen <rick@andestech.com>