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<title>u-boot.git/drivers/timer/Makefile, branch v2023.01</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
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<entry>
<title>timer: add SP804 UCLASS timer driver</title>
<updated>2022-11-02T17:58:17+00:00</updated>
<author>
<name>Andre Przywara</name>
<email>andre.przywara@arm.com</email>
</author>
<published>2022-10-20T22:10:23+00:00</published>
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<content type='text'>
The "Arm Ltd. Dual-Timer Module (SP804)" is a simple 32-bit count-down
timer IP with interrupt functionality, and is used in some SoCs from
various vendors.

Add a simple DM compliant timer driver, to allow users of the SP804 to
switch to DM_TIMER.

This relies on the input clock to be accessible via the DM clock
framework, which should be fine as we probably look at fixed-clock's
here anyway.
We re-program the control register in the probe() function, but keep
the divider in place, in case this has been set to something on purpose
before.

The TRM for the timer IP can be found here:
https://developer.arm.com/documentation/ddi0271/latest

Signed-off-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
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<pre>
The "Arm Ltd. Dual-Timer Module (SP804)" is a simple 32-bit count-down
timer IP with interrupt functionality, and is used in some SoCs from
various vendors.

Add a simple DM compliant timer driver, to allow users of the SP804 to
switch to DM_TIMER.

This relies on the input clock to be accessible via the DM clock
framework, which should be fine as we probably look at fixed-clock's
here anyway.
We re-program the control register in the probe() function, but keep
the divider in place, in case this has been set to something on purpose
before.

The TRM for the timer IP can be found here:
https://developer.arm.com/documentation/ddi0271/latest

Signed-off-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>timer: sti: convert sti-timer to arm a9 global timer</title>
<updated>2022-10-31T12:55:59+00:00</updated>
<author>
<name>William Zhang</name>
<email>william.zhang@broadcom.com</email>
</author>
<published>2022-08-24T04:44:32+00:00</published>
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<id>35751c7f3f01a6123e2965ad1b71a8e6a7a9c90d</id>
<content type='text'>
STI timer is actually ARM Cortex A9 global timer. Convert the driver to
use generic global timer name and make it consistent with Linux kernel
global timer driver. This also allows any A9 based device to use this
driver.

Signed-off-by: William Zhang &lt;william.zhang@broadcom.com&gt;
Reviewed-by: Patrice Chotard &lt;patrice.chotard@foss.st.com&gt;
Tested-by: Patrice Chotard &lt;patrice.chotard@foss.st.com&gt;
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<pre>
STI timer is actually ARM Cortex A9 global timer. Convert the driver to
use generic global timer name and make it consistent with Linux kernel
global timer driver. This also allows any A9 based device to use this
driver.

Signed-off-by: William Zhang &lt;william.zhang@broadcom.com&gt;
Reviewed-by: Patrice Chotard &lt;patrice.chotard@foss.st.com&gt;
Tested-by: Patrice Chotard &lt;patrice.chotard@foss.st.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>zynq: Convert arm twd timer to DM driver</title>
<updated>2022-09-12T10:03:17+00:00</updated>
<author>
<name>Stefan Herbrechtsmeier</name>
<email>stefan.herbrechtsmeier@weidmueller.com</email>
</author>
<published>2022-08-05T06:16:28+00:00</published>
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<id>b7e0750d8872af4f294ec46533fe5243514dcb59</id>
<content type='text'>
Move arm twd timer driver from zynq to generic location.

DM timer drivers are designed differently to original driver. Timer is
counting up and not down.
Information about clock rates are find out in timer_pre_probe() that's
why there is no need to get any additional information from DT in the
driver itself (only register offset).

Signed-off-by: Stefan Herbrechtsmeier &lt;stefan.herbrechtsmeier@weidmueller.com&gt;
Link: https://lore.kernel.org/r/20220805061629.1207-1-stefan.herbrechtsmeier-oss@weidmueller.com
Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
</content>
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<pre>
Move arm twd timer driver from zynq to generic location.

DM timer drivers are designed differently to original driver. Timer is
counting up and not down.
Information about clock rates are find out in timer_pre_probe() that's
why there is no need to get any additional information from DT in the
driver itself (only register offset).

Signed-off-by: Stefan Herbrechtsmeier &lt;stefan.herbrechtsmeier@weidmueller.com&gt;
Link: https://lore.kernel.org/r/20220805061629.1207-1-stefan.herbrechtsmeier-oss@weidmueller.com
Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>timer: add orion-timer support</title>
<updated>2022-08-23T10:39:00+00:00</updated>
<author>
<name>Michael Walle</name>
<email>michael@walle.cc</email>
</author>
<published>2022-08-17T19:37:51+00:00</published>
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<id>e9e73d78a8fb5566fdb306482945f6c9ff45c2a9</id>
<content type='text'>
Add timer support for Kirkwood and MVEBU devices.

Cc: Pali Rohár &lt;pali@kernel.org&gt;
Signed-off-by: Michael Walle &lt;michael@walle.cc&gt;
Acked-by: Pali Rohár &lt;pali@kernel.org&gt;
Reviewed-by: Stefan Roese &lt;sr@denx.de&gt;
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<pre>
Add timer support for Kirkwood and MVEBU devices.

Cc: Pali Rohár &lt;pali@kernel.org&gt;
Signed-off-by: Michael Walle &lt;michael@walle.cc&gt;
Acked-by: Pali Rohár &lt;pali@kernel.org&gt;
Reviewed-by: Stefan Roese &lt;sr@denx.de&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge tag 'xilinx-for-v2022.10' of https://source.denx.de/u-boot/custodians/u-boot-microblaze into next</title>
<updated>2022-06-27T14:15:50+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2022-06-27T14:15:50+00:00</published>
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<id>c316ee674f25b73285f241ce922307296616a92a</id>
<content type='text'>
Xilinx changes for v2022.10

cpu:
- Add driver for microblaze cpu

net:
- Add support for DM_ETH_PHY to AXI emac and emaclite

xilinx:
- Switch platforms to DM_ETH_PHY
- DT chagnes in ZynqMP and Zynq
- Enable support for SquashFS

zynqmp:
- Add support for KR260 boards
- Move BSS from address 0
- Move platform identification from board code to soc driver
- Improve zynqmp_psu_init_minimize

versal:
- Enable loading app at EL1

serial:
- Setup default address and clock rates for DEBUG uarts

pinctrl:
- Add support for tri state and output enable properties

relocate-rela:
- Clean relocate-rela implementation for ARM64
- Add support for Microblaze

microblaze:
- Add support for runtime relocation
- Rework cache handling (wiring, Kconfig) based on cpuinfo
- Remove interrupt support

timer:
- Extract axi timer driver from Microblaze to generic location
</content>
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<pre>
Xilinx changes for v2022.10

cpu:
- Add driver for microblaze cpu

net:
- Add support for DM_ETH_PHY to AXI emac and emaclite

xilinx:
- Switch platforms to DM_ETH_PHY
- DT chagnes in ZynqMP and Zynq
- Enable support for SquashFS

zynqmp:
- Add support for KR260 boards
- Move BSS from address 0
- Move platform identification from board code to soc driver
- Improve zynqmp_psu_init_minimize

versal:
- Enable loading app at EL1

serial:
- Setup default address and clock rates for DEBUG uarts

pinctrl:
- Add support for tri state and output enable properties

relocate-rela:
- Clean relocate-rela implementation for ARM64
- Add support for Microblaze

microblaze:
- Add support for runtime relocation
- Rework cache handling (wiring, Kconfig) based on cpuinfo
- Remove interrupt support

timer:
- Extract axi timer driver from Microblaze to generic location
</pre>
</div>
</content>
</entry>
<entry>
<title>microblaze: Convert axi timer to DM driver</title>
<updated>2022-06-24T12:16:32+00:00</updated>
<author>
<name>Michal Simek</name>
<email>michal.simek@amd.com</email>
</author>
<published>2022-06-24T12:16:32+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=a36d86720f23a6dd503073a82905002b88c8e363'/>
<id>a36d86720f23a6dd503073a82905002b88c8e363</id>
<content type='text'>
Move axi timer driver from Microblaze to generic location.
Origin implementation was irq based with counting down timer.

CONFIG_TIMER drivers are designed differently that timer is free running up
timer with automatic reload without any interrupt.
Information about clock rates are find out in timer_pre_probe() that's why
there is no need to get any additional information from DT in the driver
itself (only register offset).

Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
Tested-by: Ovidiu Panait &lt;ovidiu.panait@windriver.com&gt;
Link: https://lore.kernel.org/r/6c12fc86bbc1f17d05c25018862e7b7b03346b36.1654684731.git.michal.simek@amd.com
</content>
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<pre>
Move axi timer driver from Microblaze to generic location.
Origin implementation was irq based with counting down timer.

CONFIG_TIMER drivers are designed differently that timer is free running up
timer with automatic reload without any interrupt.
Information about clock rates are find out in timer_pre_probe() that's why
there is no need to get any additional information from DT in the driver
itself (only register offset).

Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
Tested-by: Ovidiu Panait &lt;ovidiu.panait@windriver.com&gt;
Link: https://lore.kernel.org/r/6c12fc86bbc1f17d05c25018862e7b7b03346b36.1654684731.git.michal.simek@amd.com
</pre>
</div>
</content>
</entry>
<entry>
<title>timer: gxp: Add HPE GXP timer support</title>
<updated>2022-06-23T01:30:04+00:00</updated>
<author>
<name>Nick Hawkins</name>
<email>nick.hawkins@hpe.com</email>
</author>
<published>2022-06-08T21:21:35+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=b25913b40ee138c35d4c92e55898a365348d5769'/>
<id>b25913b40ee138c35d4c92e55898a365348d5769</id>
<content type='text'>
Add support for the HPE GXP SOC timer. The GXP supports several different
kinds of timers but for the purpose of this driver there is only support
for the General Timer. The timer has a 1us resolution and is 56 bits.

Signed-off-by: Nick Hawkins &lt;nick.hawkins@hpe.com&gt;
</content>
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<pre>
Add support for the HPE GXP SOC timer. The GXP supports several different
kinds of timers but for the purpose of this driver there is only support
for the General Timer. The timer has a 1us resolution and is 56 bits.

Signed-off-by: Nick Hawkins &lt;nick.hawkins@hpe.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>timer: npcm: Add NPCM timer support</title>
<updated>2022-05-05T13:28:47+00:00</updated>
<author>
<name>Jim Liu</name>
<email>jim.t90615@gmail.com</email>
</author>
<published>2022-04-19T05:32:22+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=b789e4f215614e3aee2f78925683dc722ca617fc'/>
<id>b789e4f215614e3aee2f78925683dc722ca617fc</id>
<content type='text'>
Add Nuvoton BMC NPCM7xx/NPCM8xx timer driver.

Signed-off-by: Jim Liu &lt;JJLIU0@nuvoton.com&gt;
Signed-off-by: Stanley Chu &lt;yschu@nuvoton.com&gt;
</content>
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<pre>
Add Nuvoton BMC NPCM7xx/NPCM8xx timer driver.

Signed-off-by: Jim Liu &lt;JJLIU0@nuvoton.com&gt;
Signed-off-by: Stanley Chu &lt;yschu@nuvoton.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>timers: atmel_pit: introduce CONFIG_SPL_ATMEL_PIT_TIMER</title>
<updated>2022-04-26T06:54:41+00:00</updated>
<author>
<name>Eugen Hristev</name>
<email>eugen.hristev@microchip.com</email>
</author>
<published>2022-04-04T08:35:51+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=632422d4b333f3580b9fd28c424ff728ed3d3bad'/>
<id>632422d4b333f3580b9fd28c424ff728ed3d3bad</id>
<content type='text'>
This commit allows the ATMEL_PIT_TIMER driver to be unselected in SPL and be
selected in u-boot proper. The SPL can use a different timer.
By having a separate Kconfig for ATMEL_TCB in SPL, the size of the SPL
decreases by 0.3 KBytes.

Signed-off-by: Eugen Hristev &lt;eugen.hristev@microchip.com&gt;
</content>
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<pre>
This commit allows the ATMEL_PIT_TIMER driver to be unselected in SPL and be
selected in u-boot proper. The SPL can use a different timer.
By having a separate Kconfig for ATMEL_TCB in SPL, the size of the SPL
decreases by 0.3 KBytes.

Signed-off-by: Eugen Hristev &lt;eugen.hristev@microchip.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>timers: atmel_tcb: introduce CONFIG_SPL_ATMEL_TCB</title>
<updated>2022-04-26T06:53:49+00:00</updated>
<author>
<name>Eugen Hristev</name>
<email>eugen.hristev@microchip.com</email>
</author>
<published>2022-04-04T08:35:50+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=e135d2c2f385fc1cefcea64cf775c6f0267945a2'/>
<id>e135d2c2f385fc1cefcea64cf775c6f0267945a2</id>
<content type='text'>
This commit allows the ATMEL_TCB driver to be unselected in SPL and be
selected in u-boot proper. The SPL can use a different timer.
By having a separate Kconfig for ATMEL_TCB in SPL, the size of the SPL
decreases by 1 KByte.

Signed-off-by: Eugen Hristev &lt;eugen.hristev@microchip.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This commit allows the ATMEL_TCB driver to be unselected in SPL and be
selected in u-boot proper. The SPL can use a different timer.
By having a separate Kconfig for ATMEL_TCB in SPL, the size of the SPL
decreases by 1 KByte.

Signed-off-by: Eugen Hristev &lt;eugen.hristev@microchip.com&gt;
</pre>
</div>
</content>
</entry>
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