With bootstage we need access to the timer before driver model is set up.
To handle this, put the required state in global_data and provide a new
function to set up the device, separate from the driver's probe() method.

This will be used by the 'early' timer also.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Per the Intel 64 and IA-32 Architecture Software Developer's Manual,
add the reference clock for Intel Atom Processors based on the Airmont
Microarchitecture (Braswell).

This keeps in sync with Linux kernel commit:
  6fcb41c: x86/tsc_msr: Add Airmont reference clock values

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

Rename try_msr_calibrate_tsc() to cpu_mhz_from_msr(), as that
better describes what the routine does.

This keeps in sync with Linux kernel commit:
  02c0cd2: x86/tsc_msr: Remove irqoff around MSR-based TSC enumeration

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

Atom processors use a 19.2 MHz crystal oscillator.

Early processors generate 100 MHz via 19.2 MHz * 26 / 5 = 99.84 MHz.

Later processors generate 100 MHz via 19.2 MHz * 125 / 24 = 100 MHz.

Update the Silvermont-based tables accordingly, matching the Software
Developers Manual.

Also, correct a 166 MHz entry that should have been 116 MHz, and add
a missing 80 MHz entry for VLV2.

This keeps in sync with Linux kernel commit:
  05680e7: x86/tsc_msr: Correct Silvermont reference clock values

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

Some processor abbreviations in the comments of freq_desc_tables[]
are obscure. This updates part of these to mention processors
that are known to us. Also expand frequency definitions.

This keeps in sync with Linux kernel commit:
  9e0cae9: x86/tsc_msr: Update comments, expand definitions

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

If either ratio or freq is zero, the return value is zero. There
is no need to create a fail branch and return zero there.

This keeps in sync with Linux kernel commit:
  14bb4e3: x86/tsc_msr: Remove debugging messages

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

try_msr_calibrate_tsc() is currently Intel-specific, and should not
execute on any other vendor's parts.

This keeps in sync with Linux kernel commit:
  ba82683: x86/tsc_msr: Identify Intel-specific code

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

Currently we read the tsc radio like this:

	ratio = (MSR_PLATFORM_INFO >> 8) & 0x1f;

Thus we get bit 8-12 of MSR_PLATFORM_INFO, however according to the
Intel manual, the ratio bits are bit 8-15.

Fix this problem by masking 0xff instead.

This keeps in sync with Linux kernel commit:
  886123f: x86/tsc: Read all ratio bits from MSR_PLATFORM_INFO

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

Right now i8254_init() is called from timer_init() in the tsc timer
driver. But actually i8254 and tsc are completely different things.
Since tsc timer has been converted to driver model, we should find
a new place that is appropriate for U-Boot to call i8254_init(),
which is now x86_cpu_init_f().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>

To group all dm timer drivers together, move tsc timer to
drivers/timer directory.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>