<feed xmlns='http://www.w3.org/2005/Atom'>
<title>u-boot.git/drivers/timer/tsc_timer.c, branch v2018.07-rc2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>x86: tsc: add support for reading CPU freq from cpuid</title>
<updated>2018-06-13T01:50:57+00:00</updated>
<author>
<name>Christian Gmeiner</name>
<email>christian.gmeiner@gmail.com</email>
</author>
<published>2018-05-14T09:32:17+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=acc2482fd8079a062c051cfaac16054f527acab4'/>
<id>acc2482fd8079a062c051cfaac16054f527acab4</id>
<content type='text'>
Starting with cpuid level 0x16 (Skylake-based processors)
it is possible to get CPU base freq via cpuid.

This fixes booting on a skylake based system.

Signed-off-by: Christian Gmeiner &lt;christian.gmeiner@gmail.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
[bmeng: fixed wrong indention of labels]
Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Starting with cpuid level 0x16 (Skylake-based processors)
it is possible to get CPU base freq via cpuid.

This fixes booting on a skylake based system.

Signed-off-by: Christian Gmeiner &lt;christian.gmeiner@gmail.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
[bmeng: fixed wrong indention of labels]
Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>SPDX: Convert all of our single license tags to Linux Kernel style</title>
<updated>2018-05-07T13:34:12+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2018-05-06T21:58:06+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=83d290c56fab2d38cd1ab4c4cc7099559c1d5046'/>
<id>83d290c56fab2d38cd1ab4c4cc7099559c1d5046</id>
<content type='text'>
When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from.  So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry.  Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.

In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.

This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents.  There's also a few places where I found we did not have a tag
and have introduced one.

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from.  So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry.  Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.

In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.

This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents.  There's also a few places where I found we did not have a tag
and have introduced one.

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>dm: x86: Allow TSC timer to be used before DM is ready</title>
<updated>2017-09-16T06:57:44+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2017-09-06T01:49:46+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=2ff50f5fa4009adf5e23a69a4269e6bb054edd79'/>
<id>2ff50f5fa4009adf5e23a69a4269e6bb054edd79</id>
<content type='text'>
With bootstage we need access to the timer before driver model is set up.
To handle this, put the required state in global_data and provide a new
function to set up the device, separate from the driver's probe() method.

This will be used by the 'early' timer also.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
With bootstage we need access to the timer before driver model is set up.
To handle this, put the required state in global_data and provide a new
function to set up the device, separate from the driver's probe() method.

This will be used by the 'early' timer also.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>x86: tsc: Add Airmont reference clock values</title>
<updated>2017-09-16T06:57:44+00:00</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2017-08-16T05:41:50+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=3df39ef10704e82a61972fe2f71b6ff4466b7724'/>
<id>3df39ef10704e82a61972fe2f71b6ff4466b7724</id>
<content type='text'>
Per the Intel 64 and IA-32 Architecture Software Developer's Manual,
add the reference clock for Intel Atom Processors based on the Airmont
Microarchitecture (Braswell).

This keeps in sync with Linux kernel commit:
  6fcb41c: x86/tsc_msr: Add Airmont reference clock values

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Per the Intel 64 and IA-32 Architecture Software Developer's Manual,
add the reference clock for Intel Atom Processors based on the Airmont
Microarchitecture (Braswell).

This keeps in sync with Linux kernel commit:
  6fcb41c: x86/tsc_msr: Add Airmont reference clock values

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>x86: tsc: Rename try_msr_calibrate_tsc() to cpu_mhz_from_msr()</title>
<updated>2017-08-01T12:17:02+00:00</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2017-07-26T03:12:05+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=167a40166bb116a19d23c946b6394636da34f3cf'/>
<id>167a40166bb116a19d23c946b6394636da34f3cf</id>
<content type='text'>
Rename try_msr_calibrate_tsc() to cpu_mhz_from_msr(), as that
better describes what the routine does.

This keeps in sync with Linux kernel commit:
  02c0cd2: x86/tsc_msr: Remove irqoff around MSR-based TSC enumeration

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Rename try_msr_calibrate_tsc() to cpu_mhz_from_msr(), as that
better describes what the routine does.

This keeps in sync with Linux kernel commit:
  02c0cd2: x86/tsc_msr: Remove irqoff around MSR-based TSC enumeration

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>x86: tsc: Correct Silvermont reference clock values</title>
<updated>2017-08-01T12:17:02+00:00</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2017-07-26T03:12:04+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=f5757154bb2a00d529fa999da44dd18965b70738'/>
<id>f5757154bb2a00d529fa999da44dd18965b70738</id>
<content type='text'>
Atom processors use a 19.2 MHz crystal oscillator.

Early processors generate 100 MHz via 19.2 MHz * 26 / 5 = 99.84 MHz.

Later processors generate 100 MHz via 19.2 MHz * 125 / 24 = 100 MHz.

Update the Silvermont-based tables accordingly, matching the Software
Developers Manual.

Also, correct a 166 MHz entry that should have been 116 MHz, and add
a missing 80 MHz entry for VLV2.

This keeps in sync with Linux kernel commit:
  05680e7: x86/tsc_msr: Correct Silvermont reference clock values

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Atom processors use a 19.2 MHz crystal oscillator.

Early processors generate 100 MHz via 19.2 MHz * 26 / 5 = 99.84 MHz.

Later processors generate 100 MHz via 19.2 MHz * 125 / 24 = 100 MHz.

Update the Silvermont-based tables accordingly, matching the Software
Developers Manual.

Also, correct a 166 MHz entry that should have been 116 MHz, and add
a missing 80 MHz entry for VLV2.

This keeps in sync with Linux kernel commit:
  05680e7: x86/tsc_msr: Correct Silvermont reference clock values

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>x86: tsc: Update comments and expand definitions in freq_desc_tables[]</title>
<updated>2017-08-01T12:17:02+00:00</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2017-07-26T03:12:03+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=c6367748483049236d3ebdc389161f1ba472f266'/>
<id>c6367748483049236d3ebdc389161f1ba472f266</id>
<content type='text'>
Some processor abbreviations in the comments of freq_desc_tables[]
are obscure. This updates part of these to mention processors
that are known to us. Also expand frequency definitions.

This keeps in sync with Linux kernel commit:
  9e0cae9: x86/tsc_msr: Update comments, expand definitions

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Some processor abbreviations in the comments of freq_desc_tables[]
are obscure. This updates part of these to mention processors
that are known to us. Also expand frequency definitions.

This keeps in sync with Linux kernel commit:
  9e0cae9: x86/tsc_msr: Update comments, expand definitions

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>x86: tsc: Remove the fail handling in try_msr_calibrate_tsc()</title>
<updated>2017-08-01T12:17:02+00:00</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2017-07-26T03:12:02+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=fde1801eaa09adcbb26b53e53a52e5067e23d1dd'/>
<id>fde1801eaa09adcbb26b53e53a52e5067e23d1dd</id>
<content type='text'>
If either ratio or freq is zero, the return value is zero. There
is no need to create a fail branch and return zero there.

This keeps in sync with Linux kernel commit:
  14bb4e3: x86/tsc_msr: Remove debugging messages

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
If either ratio or freq is zero, the return value is zero. There
is no need to create a fail branch and return zero there.

This keeps in sync with Linux kernel commit:
  14bb4e3: x86/tsc_msr: Remove debugging messages

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>x86: tsc: Identify Intel-specific code</title>
<updated>2017-08-01T12:17:02+00:00</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2017-07-26T03:12:01+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=0b992e4932303b0a379f590f67ec9759fc97275e'/>
<id>0b992e4932303b0a379f590f67ec9759fc97275e</id>
<content type='text'>
try_msr_calibrate_tsc() is currently Intel-specific, and should not
execute on any other vendor's parts.

This keeps in sync with Linux kernel commit:
  ba82683: x86/tsc_msr: Identify Intel-specific code

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
try_msr_calibrate_tsc() is currently Intel-specific, and should not
execute on any other vendor's parts.

This keeps in sync with Linux kernel commit:
  ba82683: x86/tsc_msr: Identify Intel-specific code

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>x86: tsc: Read all ratio bits from MSR_PLATFORM_INFO</title>
<updated>2017-08-01T12:17:02+00:00</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2017-07-26T03:12:00+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=d92e9c8d313134f2ebde14a393f820b2191f4011'/>
<id>d92e9c8d313134f2ebde14a393f820b2191f4011</id>
<content type='text'>
Currently we read the tsc radio like this:

	ratio = (MSR_PLATFORM_INFO &gt;&gt; 8) &amp; 0x1f;

Thus we get bit 8-12 of MSR_PLATFORM_INFO, however according to the
Intel manual, the ratio bits are bit 8-15.

Fix this problem by masking 0xff instead.

This keeps in sync with Linux kernel commit:
  886123f: x86/tsc: Read all ratio bits from MSR_PLATFORM_INFO

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Currently we read the tsc radio like this:

	ratio = (MSR_PLATFORM_INFO &gt;&gt; 8) &amp; 0x1f;

Thus we get bit 8-12 of MSR_PLATFORM_INFO, however according to the
Intel manual, the ratio bits are bit 8-15.

Fix this problem by masking 0xff instead.

This keeps in sync with Linux kernel commit:
  886123f: x86/tsc: Read all ratio bits from MSR_PLATFORM_INFO

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
</feed>
